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* Add the SubRegIndex TableGen class.Jakob Stoklund Olesen2010-05-241-9/+11
| | | | | | | This is the beginning of purely symbolic subregister indices, but we need a bit of jiggling before the explicit numeric indices can be completely removed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104492 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminated the classification of control registers into %ecr_Sean Callanan2010-05-061-26/+11
| | | | | | | | | | and %rcr_, leaving just %cr_ which is what people expect. Updated the disassembler to support this unified register set. Added a testcase to verify that the registers continue to be decoded correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103196 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR6696 and PR6663Jim Grosbach2010-04-061-13/+25
| | | | | | | | | | | | | | | | | | | When a frame pointer is not otherwise required, and dynamic stack alignment is necessary solely due to the spilling of a register with larger alignment requirements than the default stack alignment, the frame pointer can be both used as a general purpose register and a frame pointer. That goes poorly, for obvious reasons. This patch brings back a bit of old logic for identifying the use of such registers and conservatively reserves the frame pointer during register allocation in such cases. For now, implement for X86 only since it's 32-bit linux which is hitting this, and we want a targeted fix for 2.7. As a follow-on, this will be expanded to handle other targets, as theoretically the problem could arise elsewhere as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100559 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not force indirect tailcall through fixed registers: eax, r11. Add ↵Evan Cheng2010-03-141-0/+7
| | | | | | support to allow loads to be folded to tail call instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98465 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement XMM subregs.Dan Gohman2010-02-281-18/+45
| | | | | | | | | | | | Extracting the low element of a vector is now done with EXTRACT_SUBREG, and the zero-extension performed by load movss is now modeled with SUBREG_TO_REG, and so on. Register-to-register movss and movsd are no longer considered copies; they are two-address instructions which insert a scalar into a vector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97354 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove SIL, DIL, and BPL from the GR8_NOREX allocation order also.Dan Gohman2010-01-261-11/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94560 91177308-0d34-0410-b5e6-96231b3b80d8
* SIL, DIL, BPL, and SPL require a REX prefix.Dan Gohman2010-01-261-6/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94558 91177308-0d34-0410-b5e6-96231b3b80d8
* Instruction fixes, added instructions, and AsmString changes in theSean Callanan2009-12-181-1/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
* Add RIP to GR64_NOREX. This fixed a MachineVerifier error when RIPDan Gohman2009-10-051-5/+5
| | | | | | | is used in an operand which requires GR64_NOREX. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83307 91177308-0d34-0410-b5e6-96231b3b80d8
* Added a new register class for segment registersSean Callanan2009-09-151-0/+5
| | | | | | | | | to the Intel register table. Added 16- and 64-bit MOVs to and from the segment registers to the Intel instruction tables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81895 91177308-0d34-0410-b5e6-96231b3b80d8
* Minor whitespace tidiness.Dan Gohman2009-07-301-3/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77602 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename GRAD to GR32_AD, to follow the naming convention of otherDan Gohman2009-07-301-1/+3
| | | | | | | classes. And define its SubRegClassList. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77601 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new register class to describe operands that can't be SP,Dan Gohman2009-07-301-2/+103
| | | | | | | | due to x86 encoding restrictions. This is currently off by default because it may cause code quality regressions. This is for PR4572. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77565 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminate a bunch of redundant tables.Dan Gohman2009-07-301-167/+61
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77558 91177308-0d34-0410-b5e6-96231b3b80d8
* Use array_endof instead of doing it manually.Dan Gohman2009-07-301-27/+20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77553 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a 256-bit register class and YMM registers.David Greene2009-06-291-0/+27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74469 91177308-0d34-0410-b5e6-96231b3b80d8
* add %rip to the GR64 register class. Lets avoid allocating it to anything ↵Chris Lattner2009-06-261-3/+3
| | | | | | though! :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74328 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename GR8_ABCD to GR8_ABCD_L and create GR8_ABCD_H, and use theseDan Gohman2009-04-271-9/+12
| | | | | | | | | | | | to precisely describe the h-register subreg register classes. Thanks to Jakob Stoklund Olesen for spotting this and for the initial patch! Also, make getStoreRegOpcode and getLoadRegOpcode aware of the needs of h registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70211 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename GR8_, GR16_, GR32_, and GR64_ to GR8_ABCD, GR16_ABCD,Dan Gohman2009-04-271-12/+12
| | | | | | | GR32_ABCD, and GR64_ABCD, respectively, to help describe them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70210 91177308-0d34-0410-b5e6-96231b3b80d8
* Do for GR16_NOREX what r69049 did for GR8_NOREX, to avoid trouble withDan Gohman2009-04-151-0/+35
| | | | | | | the local register allocator. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69115 91177308-0d34-0410-b5e6-96231b3b80d8
* GR8_NOREX can contain the H registers, since they don't requireDan Gohman2009-04-151-2/+3
| | | | | | | REX prefixes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69108 91177308-0d34-0410-b5e6-96231b3b80d8
* Some of GR8_NOREX registers are only available in 64-bit mode.Evan Cheng2009-04-141-0/+48
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69049 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement x86 h-register extract support.Dan Gohman2009-04-131-20/+134
| | | | | | | | | | | | | | | | | | | | | | | | | - Add patterns for h-register extract, which avoids a shift and mask, and in some cases a temporary register. - Add address-mode matching for turning (X>>(8-n))&(255<<n), where n is a valid address-mode scale value, into an h-register extract and a scaled-offset address. - Replace X86's MOV32to32_ and related instructions with the new target-independent COPY_TO_SUBREG instruction. On x86-64 there are complicated constraints on h registers, and CodeGen doesn't currently provide a high-level way to express all of them, so they are handled with a bunch of special code. This code currently only supports extracts where the result is used by a zero-extend or a store, though these are fairly common. These transformations are not always beneficial; since there are only 4 h registers, they sometimes require extra move instructions, and this sometimes increases register pressure because it can force out values that would otherwise be in one of those registers. However, this appears to be relatively uncommon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68962 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix copy+pastos in comments.Dan Gohman2009-04-131-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68958 91177308-0d34-0410-b5e6-96231b3b80d8
* List the l registers before h registers, for consistency.Dan Gohman2009-04-131-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68954 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-apply 68552.Rafael Espindola2009-04-081-0/+8
| | | | | | | | Tested by bootstrapping llvm-gcc and using that to build llvm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68645 91177308-0d34-0410-b5e6-96231b3b80d8
* Temporarily revert r68552. This was causing a failure in the self-hosting LLVMBill Wendling2009-04-071-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | builds. --- Reverse-merging (from foreign repository) r68552 into '.': U test/CodeGen/X86/tls8.ll U test/CodeGen/X86/tls10.ll U test/CodeGen/X86/tls2.ll U test/CodeGen/X86/tls6.ll U lib/Target/X86/X86Instr64bit.td U lib/Target/X86/X86InstrSSE.td U lib/Target/X86/X86InstrInfo.td U lib/Target/X86/X86RegisterInfo.cpp U lib/Target/X86/X86ISelLowering.cpp U lib/Target/X86/X86CodeEmitter.cpp U lib/Target/X86/X86FastISel.cpp U lib/Target/X86/X86InstrInfo.h U lib/Target/X86/X86ISelDAGToDAG.cpp U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h U lib/Target/X86/X86ISelLowering.h U lib/Target/X86/X86InstrInfo.cpp U lib/Target/X86/X86InstrBuilder.h U lib/Target/X86/X86RegisterInfo.td git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68560 91177308-0d34-0410-b5e6-96231b3b80d8
* Reduce code duplication on the TLS implementation.Rafael Espindola2009-04-071-0/+8
| | | | | | | | | | | | This introduces a small regression on the generated code quality in the case we are just computing addresses, not loading values. Will work on it and on X86-64 support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68552 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR3701. 1. X86 target renamed eflags register to flags. This matches ↵Evan Cheng2009-03-041-1/+1
| | | | | | what llvm-gcc generates so codegen knows flags register is being clobbered by inline asm. 2. BURR scheduler should also check if inline asm nodes can clobber "live" physical registers. Previously it was only checking target nodes with implicit defs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65996 91177308-0d34-0410-b5e6-96231b3b80d8
* Reformat the allocation-order arrays to a more conventional style.Dan Gohman2009-01-271-44/+55
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63121 91177308-0d34-0410-b5e6-96231b3b80d8
* <rdar://problem/6351057>Stuart Hastings2008-11-191-10/+12
| | | | | | | | Discourage (allocate last) use of x86_64 R12 and R13 due to their longer instruction encodings. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59644 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unneeded stuff from GRAD register class.Dale Johannesen2008-11-141-19/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59311 91177308-0d34-0410-b5e6-96231b3b80d8
* Extend InlineAsm::C_Register to allow multiple specific registersDale Johannesen2008-11-131-0/+21
| | | | | | | | | | (actually, code already all worked, only the comment changed). Use this to implement 'A' constraint on x86. Fixes PR 1779. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59266 91177308-0d34-0410-b5e6-96231b3b80d8
* Change x86 register allocation ordering to match that of gcc. Otherwise some ↵Evan Cheng2008-10-311-19/+19
| | | | | | tools get confused by prologue generated by llvm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58517 91177308-0d34-0410-b5e6-96231b3b80d8
* ATT asm printer just print register AsmName's instead of calling tolower on ↵Evan Cheng2008-07-071-112/+112
| | | | | | each charater of Name. This speeds it up by 10%. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53208 91177308-0d34-0410-b5e6-96231b3b80d8
* Add v2f32 (MMX) type to X86. Support is primitive:Dale Johannesen2008-06-241-1/+1
| | | | | | | | | load,store,call,return,bitcast. This is enough to make call and return work. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52691 91177308-0d34-0410-b5e6-96231b3b80d8
* Recommitting parts of r48130. These do not appear to cause the observed ↵Christopher Lamb2008-03-111-0/+4
| | | | | | failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48223 91177308-0d34-0410-b5e6-96231b3b80d8
* In 32-bit mode, mark 64-bit GPR's as unallocatable.Evan Cheng2008-03-111-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48217 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminate the FP_GET_ST0/FP_SET_ST0 target-specific dag nodes, just lower to Chris Lattner2008-03-101-4/+4
| | | | | | | | copyfromreg/copytoreg instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48174 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests.Evan Cheng2008-03-101-4/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48167 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow insert_subreg into implicit, target-specific values. Christopher Lamb2008-03-101-0/+4
| | | | | | | | Change insert/extract subreg instructions to be able to be used in TableGen patterns. Use the above features to reimplement an x86-64 pseudo instruction as a pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48130 91177308-0d34-0410-b5e6-96231b3b80d8
* claim ST(x) registers are 80 bits, which is true. This doesn't affect Chris Lattner2008-03-091-1/+1
| | | | | | | codegen yet because these can't be spilled (they don't exist until after RA). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48098 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename MRegisterInfo to TargetRegisterInfo.Dan Gohman2008-02-101-7/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46930 91177308-0d34-0410-b5e6-96231b3b80d8
* Provide correct DWARF register numbering for debug information emission on ↵Anton Korobeynikov2008-01-251-5/+2
| | | | | | | | | x86-32/Darwin. This should fix bunch of issues. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46337 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
* Use TableGen to emit information for dwarf register numbers. Anton Korobeynikov2007-11-111-116/+118
| | | | | | | | | This makes DwarfRegNum to accept list of numbers instead. Added three different "flavours", but only slightly tested on x86-32/linux. Please check another subtargets if possible, git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43997 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert previous rewrite per chris's comments.Dale Johannesen2007-11-091-113/+115
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43950 91177308-0d34-0410-b5e6-96231b3b80d8
* Rewrite Dwarf number handling per review comments.Dale Johannesen2007-11-091-115/+113
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43918 91177308-0d34-0410-b5e6-96231b3b80d8
* Complete conditionalization of Dwarf reg numbers.Dale Johannesen2007-11-071-35/+40
| | | | | | | | | | Would somebody not on Darwin please make sure this doesn't break anything. Exception handling failures would be the most likely symptom. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43844 91177308-0d34-0410-b5e6-96231b3b80d8
* Corrected many typing errors. And removed 'nest' parameter handlingArnold Schwaighofer2007-10-121-1/+1
| | | | | | | | | for fastcc from X86CallingConv.td. This means that nested functions are not supported for calling convention 'fastcc'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42934 91177308-0d34-0410-b5e6-96231b3b80d8
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