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* [SystemZ] Implement isLegalAddressingMode()Richard Sandiford2013-07-312-3/+21
* [SystemZ] Be more careful about inverting CC masks (conditional loads)Richard Sandiford2013-07-315-31/+31
* [SystemZ] Be more careful about inverting CC masksRichard Sandiford2013-07-319-81/+137
* [SystemZ] Move compare-and-branch generation even laterRichard Sandiford2013-07-314-136/+119
* Fixed assertion in Extract128BitVector()Elena Demikhovsky2013-07-311-1/+2
* [SystemZ] Postpone NI->RISBG conversion to convertToThreeAddress()Richard Sandiford2013-07-314-79/+193
* Added INSERT and EXTRACT intructions from AVX-512 ISA.Elena Demikhovsky2013-07-316-181/+811
* [SystemZ] Add RISBLG and RISBHG instruction definitionsRichard Sandiford2013-07-314-3/+19
* Increment arg_count inside the loop in printInline. Patch by Joe Matarazzo.Craig Topper2013-07-311-1/+1
* Changed register names (and pointer keywords) to be lower case when using Int...Craig Topper2013-07-319-230/+225
* Remove trailing whitespace and some tab characters.Craig Topper2013-07-311-9/+9
* Fixed incorrect disassembly for MOV16o16a when using Intel syntax.Craig Topper2013-07-311-2/+2
* [mips] Rename instruction DANDi to ANDi64.Akira Hatanaka2013-07-311-4/+4
* [mips] Define instruction itineraries IIArith and IILogic.Akira Hatanaka2013-07-315-38/+49
* [mips] Delete instruction format for "bal".Akira Hatanaka2013-07-301-11/+0
* [mips] Define "bal" as a pseudo instruction. Also, fix bug in the InstAlias thatAkira Hatanaka2013-07-302-5/+9
* [Sparc] Rewrite MBB's live-in registers for leaf functions. Also, addVenkatraman Govindaraju2013-07-302-7/+20
* R600/SI: Expand vector fp <-> int conversionsTom Stellard2013-07-302-4/+4
* This patch implements parsing of mips FCC register operands. The example inst...Vladimir Medic2013-07-304-14/+66
* [ARM] check bitwidth in PerformORCombineSaleem Abdulrasool2013-07-301-14/+21
* [Sparc] Use call's debugloc for the unimp instruction.Venkatraman Govindaraju2013-07-301-1/+1
* [PowerPC] Skeletal FastISel support for 64-bit PowerPC ELF.Bill Schmidt2013-07-305-1/+347
* [R600] Replicate old DAGCombiner behavior in target specific DAG combine.Quentin Colombet2013-07-301-0/+56
* [mips] Add comment and simplify function.Akira Hatanaka2013-07-291-23/+14
* Use proper section suffix for COFF weak symbolsNico Rieck2013-07-291-12/+17
* Proper va_arg/va_copy lowering on win64Nico Rieck2013-07-291-1/+3
* Allow generation of vmla.f32 instructions when targeting Cortex-A15. The patc...Silviu Baranga2013-07-294-4/+6
* test commitRobert Lytton2013-07-291-0/+1
* Added encoding prefixes for KNL instructions (EVEX).Elena Demikhovsky2013-07-2813-22/+441
* [PowerPC] Add comment explaining preprocessor directive.Bill Schmidt2013-07-281-0/+2
* Revert 187318Bill Schmidt2013-07-281-1/+1
* [PowerPC] Remove unnecessary preprocessor checking.Bill Schmidt2013-07-281-1/+1
* Create a constant pool symbol for the GOT in the ARMCGBR the same way weChandler Carruth2013-07-271-7/+8
* Fix yet another memory leak found by the vg-leak bot. Folks (includingChandler Carruth2013-07-271-2/+6
* Fix a memory leak in the hexagon scheduler. We call initialize here moreChandler Carruth2013-07-271-0/+2
* SimplifyCFG: Use parallel-and and parallel-or mode to consolidate branch cond...Tom Stellard2013-07-275-0/+110
* Revert "[PowerPC] Improve consistency in use of __ppc__, __powerpc__, etc."Rafael Espindola2013-07-261-3/+3
* [PowerPC] Improve consistency in use of __ppc__, __powerpc__, etc.Bill Schmidt2013-07-261-3/+3
* [mips] Implement llvm.trap intrinsic.Akira Hatanaka2013-07-262-0/+7
* [mips] Fix FP conditional move instructions to have explicit FP condition codeAkira Hatanaka2013-07-264-13/+14
* [mips] Fix FP branch instructions to have explicit FP condition code registerAkira Hatanaka2013-07-265-25/+41
* [mips] Increase the number of floating point condition code registers to eight.Akira Hatanaka2013-07-261-3/+5
* [mips] Fix floating point branch, comparison, and conditional move instructionsAkira Hatanaka2013-07-262-4/+4
* [mips] Delete register print method MipsInstPrinter::printCPURegs that is notAkira Hatanaka2013-07-263-11/+5
* [mips] Print instructions "beq", "bne" and "or" using assembler pseudoAkira Hatanaka2013-07-262-1/+57
* Add a target legalize hook for SplitVectorOperand (again)Justin Holewinski2013-07-261-1/+1
* Revert "Add a target legalize hook for SplitVectorOperand"Rafael Espindola2013-07-261-1/+1
* Add a target legalize hook for SplitVectorOperandJustin Holewinski2013-07-261-1/+1
* test commitRichard Osborne2013-07-261-1/+1
* [XCore] Add TODO regarding byval structsRichard Osborne2013-07-261-0/+2