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* Move to thumb2 loads, fixes a problem with incoming registersEric Christopher2010-10-081-16/+13
| | | | | | | | | as thumb1. Fixes lencod. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116027 91177308-0d34-0410-b5e6-96231b3b80d8
* reimplement the second half of the or/add optimization. We should nowChris Lattner2010-10-083-18/+51
| | | | | | | | | | | only end up emitting LEA instead of OR. If we aren't able to promote something into an LEA, we should never be emitting it as an ADD. Add some testcases that we emit "or" in cases where we used to produce an "add". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116026 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable binary encoding of some simple instructions.Jim Grosbach2010-10-081-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116022 91177308-0d34-0410-b5e6-96231b3b80d8
* Make <target>CodeEmitter::getBinaryCodeForInstr() a const method.Jim Grosbach2010-10-084-8/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116018 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the new TB_NOT_REVERSABLE flag instead of special Chris Lattner2010-10-081-20/+26
| | | | | | | casing FsMOVAPDrr/FsMOVAPSrr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116016 91177308-0d34-0410-b5e6-96231b3b80d8
* simplify some map operations.Chris Lattner2010-10-072-16/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116014 91177308-0d34-0410-b5e6-96231b3b80d8
* Reimplement (part of) the or -> add optimization. Matching 'or' into 'add'Chris Lattner2010-10-074-65/+126
| | | | | | | | | | | | | | | | | | | | | is general goodness because it allows ORs to be converted to LEA to avoid inserting copies. However, this is bad because it makes the generated .s file less obvious and gives valgrind heartburn (tons of false positives in bitfield code). While the general fix should be in valgrind, we can at least try to avoid emitting ADD instructions that *don't* get promoted to LEA. This is more work because it requires introducing pseudo instructions to represents "add that knows the bits are disjoint", but hey, people really love valgrind. This fixes this testcase: https://bugs.kde.org/show_bug.cgi?id=242137#c20 the add r/i cases are coming next. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116007 91177308-0d34-0410-b5e6-96231b3b80d8
* Code refactoring.Evan Cheng2010-10-072-104/+160
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116002 91177308-0d34-0410-b5e6-96231b3b80d8
* Reduce casting in various tables by defining the tableChris Lattner2010-10-072-27/+26
| | | | | | | with the right types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116001 91177308-0d34-0410-b5e6-96231b3b80d8
* simplify code: don't build up vector only to assert it is empty.Chris Lattner2010-10-071-8/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115997 91177308-0d34-0410-b5e6-96231b3b80d8
* Now with fewer extraneous semicolons!Owen Anderson2010-10-071-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115996 91177308-0d34-0410-b5e6-96231b3b80d8
* Trivial MC code emitter shell. No instruction forms actually handled yet.Jim Grosbach2010-10-071-3/+19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115993 91177308-0d34-0410-b5e6-96231b3b80d8
* Include the auto-generated bits for machine encoding.Jim Grosbach2010-10-071-0/+20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115987 91177308-0d34-0410-b5e6-96231b3b80d8
* Remember to promote load/store types for stack to register size.Eric Christopher2010-10-071-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115984 91177308-0d34-0410-b5e6-96231b3b80d8
* convert test to use the existing classes that the multipatternsChris Lattner2010-10-071-99/+48
| | | | | | | | | | use. Since TEST is completely different than all other binops, don't define a multipattern for it. This completes factorization of binops. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115982 91177308-0d34-0410-b5e6-96231b3b80d8
* convert cmp to use a multipatternChris Lattner2010-10-071-199/+181
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115978 91177308-0d34-0410-b5e6-96231b3b80d8
* Canonicalize X86ISD::MOVDDUP nodes to v2f64 to make sure all cases match. ↵Evan Cheng2010-10-072-16/+22
| | | | | | Also eliminate unneeded isel patterns. rdar://8520311 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115977 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM instruction don't have instruction prefixes, so remove the helper functionsJim Grosbach2010-10-071-16/+1
| | | | | | for them from the MCCodeEmitter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115975 91177308-0d34-0410-b5e6-96231b3b80d8
* reduce redundancy between pattern copies.Chris Lattner2010-10-071-49/+53
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115968 91177308-0d34-0410-b5e6-96231b3b80d8
* the opcode for BinOpMI/BinOpMI8 is always the same, remove the argument.Chris Lattner2010-10-071-19/+19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115967 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve comment.Owen Anderson2010-10-071-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115966 91177308-0d34-0410-b5e6-96231b3b80d8
* convert adc/sbb to a multipattern. Because the adde/sube nodes Chris Lattner2010-10-071-310/+150
| | | | | | | | | | | | are not defined as returning EFLAGS (like add_flag and friends), the entire multipattern and several of the subclasses need to be cloned. This could be handled through better instantiation support in tblgen, but it isn't meta enough. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115964 91177308-0d34-0410-b5e6-96231b3b80d8
* Add initialization routines for Target.Owen Anderson2010-10-071-2/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115957 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix obvious mistake pointed out by Michael Spencer.Jakob Stoklund Olesen2010-10-071-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115952 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the missing cases to the type->registerclass conversion function.Kalle Raiskila2010-10-071-0/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115921 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement two virtual functions in SPUTargetLowering.Kalle Raiskila2010-10-072-0/+31
| | | | | | | | | | | | Before the implementation of isLegalAddressingMode, some rare cases of code were miscompiled if optimized with the LoopStrengthReduce pass. It is unclear (to me) if LSR is "allowed" to produce wrong code with a bad TargetLowering, or if the bug is elsewhere and this patch just hides it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115919 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the correct register class for load instructions - fixesEric Christopher2010-10-071-1/+8
| | | | | | | compilation of MultiSource/Benchmarks/Bullet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115907 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the correct register class here.Eric Christopher2010-10-071-1/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115906 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the thumb2 conditional move instruction.Eric Christopher2010-10-071-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115905 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove in-progress assertion, add TODO.Eric Christopher2010-10-071-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115904 91177308-0d34-0410-b5e6-96231b3b80d8
* Model operand cycles of vldm / vstm; also fixes scheduling itineraries of ↵Evan Cheng2010-10-077-42/+143
| | | | | | vldr / vstr, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115898 91177308-0d34-0410-b5e6-96231b3b80d8
* add support for isConvertibleToThreeAddress to ArithBinOpEFLAGS,Chris Lattner2010-10-071-178/+18
| | | | | | | allowing us to convert ADD over. deletes 160 lines of .td file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115897 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a few issues in ArithBinOpEFLAGS that made it specific to and.Chris Lattner2010-10-071-497/+18
| | | | | | | | | | Start using ArithBinOpEFLAGS for OR, XOR, and SUB. This removes 500 lines from the .td file. Now AND/OR/XOR/SUB are all defined exactly the same way instead of being close relatives. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115896 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert 'and' to single instance of a multipatternChris Lattner2010-10-071-50/+63
| | | | | | | | | | | | | which instantiates the 34 versions of and all in one swoop. The BaseOpc/BaseOpc2/BaseOpc4 stuff should not be required, but tblgen's feeble brain explodes when I use Or4<BaseOpc>.V in the multipattern. No change in the generated .inc files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115893 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow use of the 16-bit literal move instruction in CMOVs for Thumb2 mode.Jim Grosbach2010-10-072-7/+20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115890 91177308-0d34-0410-b5e6-96231b3b80d8
* add a new BinOpAI class to represent the immediate form that directly acts ↵Chris Lattner2010-10-071-10/+16
| | | | | | | | | | | on EAX. This does change the generated .inc files to include the implicit use/def of eax. Since these instructions are only generated by the assembler and disassembler it doesn't actually matter though. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115885 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow use of the 16-bit literal move instruction in CMOVs for ARM mode.Jim Grosbach2010-10-072-8/+23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115884 91177308-0d34-0410-b5e6-96231b3b80d8
* add a bunch of classes for other common patterns.Chris Lattner2010-10-071-60/+51
| | | | | | | As usual, no change in generated .inc files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115882 91177308-0d34-0410-b5e6-96231b3b80d8
* Define a new BinOpRI8 class and use it to define the imm8 versions of and.Chris Lattner2010-10-071-27/+43
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115880 91177308-0d34-0410-b5e6-96231b3b80d8
* Constrain the offset register to a *_NOSP register class when inserting LEAJakob Stoklund Olesen2010-10-071-2/+35
| | | | | | | | instructions. This unbreaks the machine code verifier and fixes PR8317. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115879 91177308-0d34-0410-b5e6-96231b3b80d8
* add the pattern operator to match to X86TypeInfo, use this to Chris Lattner2010-10-071-11/+11
| | | | | | | convert AND64ri32 to use BinOpRI. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115878 91177308-0d34-0410-b5e6-96231b3b80d8
* Properly handle GR32_NOSP in X86RegisterInfo::getMatchingSuperRegClass.Jakob Stoklund Olesen2010-10-061-1/+6
| | | | | | This function looks like it is about ready to be generated by TebleGen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115876 91177308-0d34-0410-b5e6-96231b3b80d8
* remove trailing whitespaceJim Grosbach2010-10-061-5/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115860 91177308-0d34-0410-b5e6-96231b3b80d8
* First in a sequence of ARM/MC/*ELF* specific work.Jason W Kim2010-10-062-39/+60
| | | | | | | | | | | Lifted the EmitRawText calls to ARMAsmPrinter::emitAttribute() Added ARMAsmPrinter::emitAttributes() (plural s). TODO: .cpu attribute needs to be refactored git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115859 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up MOVi32imm and t2MOVi32imm pseudo instruction definitions.Jim Grosbach2010-10-063-7/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115853 91177308-0d34-0410-b5e6-96231b3b80d8
* Kill of the vestiges of the 'call' Modifier (no longer needed for PLT).Jim Grosbach2010-10-064-21/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115845 91177308-0d34-0410-b5e6-96231b3b80d8
* Now that VDUPfqf and VDUPfdfare properly pseudos, kill the no-longer-neededJim Grosbach2010-10-062-40/+3
| | | | | | | | "lane" operand modifier. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115843 91177308-0d34-0410-b5e6-96231b3b80d8
* Change the NEON VDUPfdf and VDUPfqf pseudo-instructions to actually beJim Grosbach2010-10-062-7/+28
| | | | | | | | pseudo instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115840 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a 'pattern' arg to the ARM PseudoNeonI class.Jim Grosbach2010-10-062-7/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115831 91177308-0d34-0410-b5e6-96231b3b80d8
* target operand flag values aren't a bitmaskJim Grosbach2010-10-061-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115798 91177308-0d34-0410-b5e6-96231b3b80d8
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