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* The vbroadcast family of instructions has 'fallback patterns' in case where theNadav Rotem2012-07-181-6/+8
* Mips specific inline asm operand modifier 'M':Jack Carter2012-07-181-3/+8
* Remove tab characters.Craig Topper2012-07-181-13/+13
* Fix typo in error message and remove some tab characters.Craig Topper2012-07-181-5/+5
* Make x86 asm parser to check for xmm vs ymm for index register in gather inst...Craig Topper2012-07-183-15/+66
* More replacing of target-dependent intrinsics with target-indepdent Joel Jones2012-07-181-2/+2
* Clean up Mips16InstrFormats.td and Mips16InstrInfo.td.Akira Hatanaka2012-07-172-93/+117
* Back out r160101 and instead implement a dag combine to recover from instcomb...Evan Cheng2012-07-171-0/+1
* Implement r160312 as target indepedenet dag combine.Evan Cheng2012-07-171-44/+0
* This is another case where instcombine demanded bits optimization createdEvan Cheng2012-07-172-0/+20
* For something likeEvan Cheng2012-07-161-0/+44
* Revert "AMDGPU: Add core backend files for R600/SI codegen v6"Tom Stellard2012-07-16114-28329/+0
* Revert "Build script changes for R600/SI Codegen v6"Tom Stellard2012-07-161-1/+1
* Revert "Target/AMDGPU/R600KernelParameters.cpp: Fix two includes, <llvm/IRBui...Tom Stellard2012-07-161-2/+2
* Revert "Target/AMDGPU: [CMake] Fix dependencies. 1) Add intrinsics_gen. Add A...Tom Stellard2012-07-162-3/+1
* Revert "Target/AMDGPU/R600KernelParameters.cpp: Don't use "and", "or" as cond...Tom Stellard2012-07-161-8/+8
* Revert "Target/AMDGPU/AMDILIntrinsicInfo.cpp: Use llvm_unreachable() in nonre...Tom Stellard2012-07-161-1/+1
* Revert "Target/AMDGPU: Fix includes, or msvc build failed."Tom Stellard2012-07-162-2/+2
* With r160248 in place this code is no longer needed.Chad Rosier2012-07-162-17/+1
* Target/AMDGPU: Fix includes, or msvc build failed.NAKAMURA Takumi2012-07-162-2/+2
* Target/AMDGPU/AMDILIntrinsicInfo.cpp: Use llvm_unreachable() in nonreturn fun...NAKAMURA Takumi2012-07-161-1/+1
* Target/AMDGPU/R600KernelParameters.cpp: Don't use "and", "or" as conditional ...NAKAMURA Takumi2012-07-161-8/+8
* Doubleword Shift Left Logical Plus 32Jack Carter2012-07-164-1/+57
* Target/AMDGPU: [CMake] Fix dependencies. 1) Add intrinsics_gen. Add AMDGPUCom...NAKAMURA Takumi2012-07-162-1/+3
* Target/AMDGPU/R600KernelParameters.cpp: Fix two includes, <llvm/IRBuilder.h> ...NAKAMURA Takumi2012-07-161-2/+2
* Build script changes for R600/SI Codegen v6Tom Stellard2012-07-161-1/+1
* AMDGPU: Add core backend files for R600/SI codegen v6Tom Stellard2012-07-16114-0/+28329
* Fix a bug in the 3-address conversion of LEA when one of the operands is anNadav Rotem2012-07-161-0/+7
* This CL changes the function prologue and epilogue emitted on X86 when stack ...Alexey Samsonov2012-07-161-53/+47
* Teach getTargetVShiftNode about TargetConstant nodes.Nadav Rotem2012-07-151-1/+4
* Rename VBROADCASTSDrm into VBROADCASTSDYrm to match the naming convention.Nadav Rotem2012-07-152-3/+8
* AVX: Fix a bug in getTargetVShiftNode. The shift amount has to be a 128bit ve...Nadav Rotem2012-07-141-1/+7
* This is one of the first steps at moving to replace target-dependent Joel Jones2012-07-131-1/+1
* Remove variable_ops from call instructions in most targets.Jakob Stoklund Olesen2012-07-1311-46/+44
* Remove variable_ops from ARM call instructions.Jakob Stoklund Olesen2012-07-133-22/+19
* The Mips specific relocation R_MIPS_GOT_DISP Jack Carter2012-07-134-4/+12
* Make helper functions static.Benjamin Kramer2012-07-131-1/+1
* Mark VINSERTI128rm as MayLoad=1. Fixes PR13348.Craig Topper2012-07-131-2/+2
* Give the rdrand instructions a SideEffect flag and a chain so MachineCSE and ...Benjamin Kramer2012-07-122-4/+5
* Add intrinsics for Ivy Bridge's rdrand instruction.Benjamin Kramer2012-07-123-3/+49
* Update GATHER instructions to support 2 read-write operands. Patch from mysel...Craig Topper2012-07-124-16/+44
* ARM: fix typo in commentsManman Ren2012-07-111-1/+1
* ARM: Fix optimizeCompare to correctly check safe condition.Manman Ren2012-07-111-9/+14
* Patch for Mips direct object generation.Jack Carter2012-07-111-0/+8
* This change removes an "initialization" warning.Jack Carter2012-07-111-4/+3
* In register classes in MipsRegisterInfo.td, list the registers in ascendingAkira Hatanaka2012-07-111-99/+114
* [x86 fast-isel] Per discussion with Eric, add all cases to switch with verboseChad Rosier2012-07-111-1/+8
* X86: Update to peephole optimization to move Movr0 before (Sub, Cmp) pair.Manman Ren2012-07-111-1/+22
* Implement MipsTargetLowering::LowerSELECT_CC to custom lower SELECT_CC.Akira Hatanaka2012-07-112-3/+17
* [x86 fast-isel] Rather then call llvm_unreachable() have fast-isel fall backChad Rosier2012-07-111-1/+1
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