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* Refactor loop for better readability.Jim Grosbach2012-01-311-3/+2
| | | | | | Excellent suggestion from Ben Kramer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149417 91177308-0d34-0410-b5e6-96231b3b80d8
* Add explanatory comment.Jim Grosbach2012-01-311-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149416 91177308-0d34-0410-b5e6-96231b3b80d8
* Add assembler dialect attribute in asm parser which lets target specific asm ↵Devang Patel2012-01-311-4/+3
| | | | | | parser change dialect on the fly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149396 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove pcmpgt/pcmpeq intrinsics as clang is not using them.Craig Topper2012-01-311-20/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149367 91177308-0d34-0410-b5e6-96231b3b80d8
* with recent changes, ConstantArray is never a "string". Remove the associatedChris Lattner2012-01-312-96/+25
| | | | | | | methods and constant fold the clients to false. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149362 91177308-0d34-0410-b5e6-96231b3b80d8
* use the right accessor for ConstantDataArray.Chris Lattner2012-01-311-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149342 91177308-0d34-0410-b5e6-96231b3b80d8
* PR11834: Use macros which are defined on Windows. Patch by Marina Yatsina.Evan Cheng2012-01-302-2/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149294 91177308-0d34-0410-b5e6-96231b3b80d8
* Intel syntax. Adjust special code, used to recognize cmp<comparison ↵Devang Patel2012-01-301-2/+4
| | | | | | code>{ss,sd,ps,pd}, for intel syntax. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149291 91177308-0d34-0410-b5e6-96231b3b80d8
* Intel syntax. Support .intel_syntax directive.Devang Patel2012-01-301-10/+24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149270 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix refacto.Benjamin Kramer2012-01-301-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149269 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminate narrowing conversion in initializer list, to make C++11 happyDouglas Gregor2012-01-301-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149254 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Simplify shuffle mask generation code.Benjamin Kramer2012-01-301-53/+34
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149248 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix pattern for memory form of PSHUFD for use with FP vectors to remove ↵Craig Topper2012-01-302-10/+3
| | | | | | bitcast to an integer vector that normal code wouldn't have. Also remove bitcasts from code that turns splat vector loads into a shuffle as it was making the broken pattern necessary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149232 91177308-0d34-0410-b5e6-96231b3b80d8
* Move some XOP patterns into instruction definition. Replae VPCMOV intrinsic ↵Craig Topper2012-01-304-452/+252
| | | | | | patterns with custom lowering to a target specific nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149216 91177308-0d34-0410-b5e6-96231b3b80d8
* Cleanups for EABI standard functionsAnton Korobeynikov2012-01-291-2/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149195 91177308-0d34-0410-b5e6-96231b3b80d8
* Use base AAPCS for varargs functions even for AAPCS-VFP CCAnton Korobeynikov2012-01-291-1/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149194 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a note about a potential optimization for clz/ctz patterns for ARMBob Wilson2012-01-281-0/+16
| | | | | | (and other targets). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149182 91177308-0d34-0410-b5e6-96231b3b80d8
* Ensure .AliasedSymbol() is called on all uses of getSymbol(). Affects ARM ↵James Molloy2012-01-282-2/+2
| | | | | | | | | | and MIPS ELF backends. Fixes PR11877 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149180 91177308-0d34-0410-b5e6-96231b3b80d8
* Intel Syntax: Parse mem operand with seg reg. QWORD PTR FS:[320]Devang Patel2012-01-271-3/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149142 91177308-0d34-0410-b5e6-96231b3b80d8
* Move some patterns back near their instructions and use AddedComplexity to ↵Craig Topper2012-01-271-49/+41
| | | | | | fix priority. Merge some patterns into their instruction definition. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149122 91177308-0d34-0410-b5e6-96231b3b80d8
* Keep source location information for X86 MCFixup's.Jim Grosbach2012-01-272-18/+23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149106 91177308-0d34-0410-b5e6-96231b3b80d8
* Better user diagnostics for more ARM MachO relocation errors.Jim Grosbach2012-01-271-4/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149102 91177308-0d34-0410-b5e6-96231b3b80d8
* Better diagnostic for malformed .org assembly directive.Jim Grosbach2012-01-271-3/+3
| | | | | | Provide source line number information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149101 91177308-0d34-0410-b5e6-96231b3b80d8
* Keep source information, if available, around for ARM Fixups.Jim Grosbach2012-01-263-9/+15
| | | | | | | | | | | | | | | | | Adjust an example MachObjectWriter diagnostic to use the information to issue a better message. Before: LLVM ERROR: unknown ARM fixup kind! After: x.s:6:5: error: unsupported relocation on symbol beq bar ^ rdar://9800182 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149093 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle call-clobbered ymm registers on Win64.Jakob Stoklund Olesen2012-01-262-1/+8
| | | | | | | | | | | | | | The Win64 calling convention has xmm6-15 as callee-saved while still clobbering all ymm registers. Add a YMM_HI_6_15 pseudo-register that aliases the clobbered part of the ymm registers, and mark that as call-clobbered. This allows live xmm registers across calls. This hack wouldn't be necessary with RegisterMask operands representing the call clobbers, but they are not quite operational yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149088 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up. Fix mismatched return types for error handling.Jim Grosbach2012-01-261-8/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149062 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for the R_ARM_TARGET1 relocation, which should be given to ↵James Molloy2012-01-263-1/+21
| | | | | | | | | | relocations applied to all C++ constructors and destructors. This enables the linker to match concrete relocation types (absolute or relative) with whatever library or C++ support code is being linked against. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149057 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix for the following bug in AVX codegen for double-to-int conversions:Victor Umansky2012-01-261-2/+2
| | | | | | | | | | | | | | | . "fptosi" and "fptoui" IR instructions are defined with round-to-zero rounding mode. . Currently for AVX mode for <4xdouble> and <8xdouble> the "VCVTPD2DQ.128" and "VCVTPD2DQ.256" instructions are selected (for .fp_to_sint. DAG node operation ) by AVX codegen. However they use round-to-nearest-even rounding mode. . Consequently, the conversion produces incorrect numbers. The fix is to replace selection of VCVTPD2DQ instructions with VCVTTPD2DQ instructions. The latter use truncate (i.e. round-to-zero) rounding mode. As .fp_to_sint. DAG node operation is used only for lowering of "fptosi" and "fptoui" IR instructions, the fix in X86InstrSSE.td definition file doesn.t have an impact on other LLVM flows. The patch includes changes in the .td file, LIT test for the changes and a fix in a legacy LIT test (which produced asm code conflicting with LLVN IR spec). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149056 91177308-0d34-0410-b5e6-96231b3b80d8
* Add HasXOP predicate check covering a bunch of XOP intrinsic patterns.Craig Topper2012-01-261-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149054 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix AVX vs SSE patterns ordering issue for VPCMPESTRM and VPCMPISTRM.Craig Topper2012-01-261-2/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149053 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some more patterns by custom lowering intrinsics to target specific ↵Craig Topper2012-01-262-25/+14
| | | | | | nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149052 91177308-0d34-0410-b5e6-96231b3b80d8
* Properly emit ctors / dtors with priorities into desired sectionsAnton Korobeynikov2012-01-252-2/+37
| | | | | | | | | | and let linker handle the rest. This finally fixes PR5329 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148990 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assemly parsing and validation of IT instruction.Jim Grosbach2012-01-252-3/+14
| | | | | | | | | | "Although a Thumb2 instruction, the IT mnemonic shall be permitted in ARM mode, and the condition verified to match the condition code(s) on the following instruction(s)." PR11853 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148969 91177308-0d34-0410-b5e6-96231b3b80d8
* fix a bug I introduced in r148929, this is not a splat!Chris Lattner2012-01-251-1/+5
| | | | | | | Thanks to Eli for noticing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148947 91177308-0d34-0410-b5e6-96231b3b80d8
* Custom lower PSIGN and PSHUFB intrinsics to their corresponding target ↵Craig Topper2012-01-254-74/+49
| | | | | | specific nodes so we can remove the isel patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148933 91177308-0d34-0410-b5e6-96231b3b80d8
* use ConstantVector::getSplat in a few places.Chris Lattner2012-01-251-24/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148929 91177308-0d34-0410-b5e6-96231b3b80d8
* Custom lower phadd and phsub intrinsics to target specific nodes. Remove the ↵Craig Topper2012-01-253-63/+70
| | | | | | patterns that are no longer necessary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148927 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove AVX 256-bit unaligned load intrinsics. 128-bit versions had been ↵Craig Topper2012-01-251-4/+0
| | | | | | removed a while ago. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148922 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark 64-bit register RA_64 unused too.Akira Hatanaka2012-01-251-4/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148918 91177308-0d34-0410-b5e6-96231b3b80d8
* Modify MipsFrameLowering::emitPrologue and emitEpilogue.Akira Hatanaka2012-01-251-78/+68
| | | | | | | | | | | | - Use MipsAnalyzeImmediate to expand immediates that do not fit in 16-bit. - Change the types of variables so that they are sufficiently large to handle 64-bit pointers. - Emit instructions to set register $28 in a function prologue after instructions which store callee-saved registers have been emitted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148917 91177308-0d34-0410-b5e6-96231b3b80d8
* Modify MipsRegisterInfo::eliminateFrameIndex to use MipsAnalyzeImmediate toAkira Hatanaka2012-01-251-12/+34
| | | | | | | | | | expand offsets that do not fit in the 16-bit immediate field of load and store instructions. Also change the types of variables so that they are sufficiently large to handle 64-bit pointers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148916 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge intrinsic pattern and no pattern versions of VCVTSD2SI intruction ↵Craig Topper2012-01-251-24/+5
| | | | | | definitions. Matches non-AVX version of same instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148914 91177308-0d34-0410-b5e6-96231b3b80d8
* MipsAnalyzeImmediate.h: Fix to add DataTypes.h for msvc.NAKAMURA Takumi2012-01-251-0/+1
| | | | | | inttypes.h is not supplied in msvc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148912 91177308-0d34-0410-b5e6-96231b3b80d8
* Target/Mips: Unbreak CMake build.NAKAMURA Takumi2012-01-251-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148909 91177308-0d34-0410-b5e6-96231b3b80d8
* Lower 64-bit immediates using MipsAnalyzeImmediate that has just been added. Akira Hatanaka2012-01-252-31/+42
| | | | | | | | Add a test case to show fewer instructions are needed to load an immediate with the new way of loading immediates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148908 91177308-0d34-0410-b5e6-96231b3b80d8
* Add class MipsAnalyzeImmediate which comes up with an instruction sequence toAkira Hatanaka2012-01-252-0/+215
| | | | | | | | load an immediate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148900 91177308-0d34-0410-b5e6-96231b3b80d8
* NEON VLD4(all lanes) assembly parsing and encoding.Jim Grosbach2012-01-254-2/+215
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148884 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up. Rename VLD4DUP patterns for consistency.Jim Grosbach2012-01-241-6/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148883 91177308-0d34-0410-b5e6-96231b3b80d8
* NEON VLD3(all lanes) assembly parsing and encoding.Jim Grosbach2012-01-244-6/+212
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148882 91177308-0d34-0410-b5e6-96231b3b80d8
* Sign-extend 32-bit integer arguments when they are passed in 64-bit registers,Akira Hatanaka2012-01-241-1/+4
| | | | | | | | which is what N32/64 does. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148875 91177308-0d34-0410-b5e6-96231b3b80d8
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