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* Revert r194865 and r194874.Alexey Samsonov2013-11-1858-199/+44
* [AArch64 NEON]Add mov alias for simd copy instructions.Kevin Qin2013-11-181-35/+63
* Implement the newly added ACLE functions for ld1/st1 with 2/3/4 vectors.Hao Liu2013-11-184-45/+237
* Added a size field to the stack map record to handle subregister spills.Andrew Trick2013-11-173-12/+41
* The WebKit_JS CC preserves the same registers as the C CC.Juergen Ributzka2013-11-161-0/+1
* R600: Make dot_4 instructions predicableVincent Lejeune2013-11-161-0/+19
* X86: Encode the 'h' cpu subtype in the MachO header for x86.Jim Grosbach2013-11-161-6/+14
* Implemented aarch64 Neon scalar vmulx_lane intrinsicsAna Pazos2013-11-151-2/+169
* Remove unused arguments.Lang Hames2013-11-151-4/+2
* During folding for patchpoint/stackmap instructions, defer creation of new MIsLang Hames2013-11-151-4/+5
* [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-1558-44/+199
* Make method staticMatt Arsenault2013-11-152-2/+2
* [AArch64] Fix the scalar NEON ACLE functions so that they return float/doubleChad Rosier2013-11-151-4/+4
* Avoid illegal integer promotion in fastiselBob Wilson2013-11-153-21/+6
* R600/SI: Add VReg_96 register class to SIRegisterInfo::hasVGPRs()Tom Stellard2013-11-151-0/+1
* Add AVX512 unmasked FMA intrinsics and support.Cameron McInally2013-11-151-1/+25
* [mips][msa] lowerMSABitClear() should use SelectionDAG::getNOT() instead of u...Daniel Sanders2013-11-151-14/+2
* Hopefully fix uninitialized memory read in AArch64AsmParser found by MSan boo...Alexey Samsonov2013-11-151-5/+5
* Fix illegal DAG produced by SelectionDAG::getConstant() for v2i64 typeDaniel Sanders2013-11-151-59/+91
* [NVPTX] Fix handling of indirect callsJustin Holewinski2013-11-156-12/+46
* Use instr mapping for microMIPS in llvm-mc.Zoran Jovanovic2013-11-152-5/+9
* Add target hook to prevent folding some bitcasted loads.Matt Arsenault2013-11-152-0/+13
* [llvm-c] Make LLVMGetTargetFromName actually workPeter Zotov2013-11-151-1/+2
* [llvm-c] Add missing const qualifiers to LLVMCreateTargetMachinePeter Zotov2013-11-151-3/+4
* [llvm-c] Simplify signature of LLVMGetTargetFromNamePeter Zotov2013-11-151-7/+4
* Make all the conditional Mips 16 branches get initially set for theReed Kotler2013-11-153-28/+46
* Add addrspacecast instruction.Matt Arsenault2013-11-153-2/+11
* R600: Fix scheduling of instructions that use the LDS output queueTom Stellard2013-11-159-51/+116
* R600/SI: Add processor type for HawaiiTom Stellard2013-11-141-0/+1
* R600/SI: Remove redundant legalizeOperands callMatt Arsenault2013-11-141-1/+0
* Add #include raw_ostream.h in lib/Target/R600/SIFixSGPRCopies.cppHans Wennborg2013-11-141-0/+1
* R600/SI: Specify S_ADDK/S_MULK set SCC and are commutableMatt Arsenault2013-11-141-2/+5
* [AArch64] Remove redundant Neon_immAllOnes/Neon_immAllZeros leaf patterns.Chad Rosier2013-11-141-25/+9
* ARM: produce friendly error for invalid inline asmTim Northover2013-11-141-0/+4
* AVX-512: Handled extractelement from mask vector;Elena Demikhovsky2013-11-143-2/+80
* Indentation fixesMatt Arsenault2013-11-142-3/+2
* Add a commentMatt Arsenault2013-11-141-1/+3
* Fix trailing whitespace in debug printingMatt Arsenault2013-11-141-1/+1
* AArch64DAGToDAGISel::SelectVTBL(): Fix a warning. [-Wunused-variable]NAKAMURA Takumi2013-11-141-3/+1
* Minor extension to llvm.experimental.patchpoint: don't require a call.Andrew Trick2013-11-141-11/+16
* Don't mangle \n and "Rafael Espindola2013-11-141-35/+1
* R600/SIFixSGPRCopies.cpp: Fix \param to \return. [-Wdocumentation]NAKAMURA Takumi2013-11-141-1/+1
* Whitespace.NAKAMURA Takumi2013-11-141-4/+4
* [AArch64 neon] support poly64 and relevant intrinsic functions.Kevin Qin2013-11-141-0/+9
* Implement aarch64 neon instruction class SIMD misc.Kevin Qin2013-11-143-17/+957
* Implement AArch64 NEON instruction set AdvSIMD (table).Jiangning Liu2013-11-143-0/+168
* R600: Fix uninitialized variable usageTom Stellard2013-11-131-5/+5
* Take care of long short branch immediate instructions for mips16 inReed Kotler2013-11-131-5/+10
* R600/SI: Add support for private address space load/storeTom Stellard2013-11-1324-134/+402
* R600/SI: Prefer SALU instructions for bit shift operationsTom Stellard2013-11-139-35/+528
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