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* The logic for breaking the CFG in the presence of hot successors didn'tChandler Carruth2011-11-201-3/+29
* SCEV: Actually set overflow flags on add expressions.Benjamin Kramer2011-11-201-2/+2
* Add code for lowering v32i8 shifts by a splat to AVX2 immediate shift instruc...Craig Topper2011-11-202-45/+45
* Use 256-bit vcmpeqd for creating an all ones vector when AVX2 is enabled.Craig Topper2011-11-194-16/+33
* Remove some of the special classes that worked around an old tablegen limitat...Craig Topper2011-11-191-100/+50
* Custom lower AVX2 variable shift intrinsics to shl/srl/sra nodes and remove t...Craig Topper2011-11-192-74/+42
* Move the handling of unanalyzable branches out of the loop-driven chainChandler Carruth2011-11-191-25/+33
* Synthesize SSSE3/AVX 128-bit horizontal integer add/sub instructions from add...Craig Topper2011-11-194-3/+62
* Collapse X86 PSIGNB/PSIGNW/PSIGND node types.Craig Topper2011-11-194-33/+18
* Extend VPBLENDVB and VPSIGN lowering to work for AVX2.Craig Topper2011-11-193-111/+127
* Remove unused parameters from the AVX maskmov classes.Craig Topper2011-11-191-12/+6
* Fix a corner case in updating LoopInfo after fully unrolling an outer loop.Andrew Trick2011-11-181-11/+9
* Add AVX2 vpbroadcast supportNadav Rotem2011-11-182-28/+62
* [asan] workaround for reg alloc bug 11395: don't instrument functions with la...Kostya Serebryany2011-11-181-0/+13
* Guard call to getRegForValue with isTypeLegal check to avoid unnecessary work...Chad Rosier2011-11-181-3/+5
* DISubrange supports unsigned lower/upper array bounds, so let's not fake it i...Devang Patel2011-11-171-4/+4
* quick fix: remove GlobalVariable::GlobalVariable mistakenly commited at r1449...Kostya Serebryany2011-11-171-3/+3
* Fix an overly general check in SimplifyIndvar to handle useless phi cycles.Andrew Trick2011-11-171-2/+2
* fall back to explicit list of allowed linkages when instrumenting globals in ...Kostya Serebryany2011-11-171-2/+5
* Add TODO comment.Chad Rosier2011-11-171-0/+2
* Fix SSE/AVX integer comparison patterns to understand that all integer vector...Craig Topper2011-11-171-24/+42
* Dead code.Chad Rosier2011-11-171-14/+0
* When fast iseling a GEP, accumulate the offset rather than emitting a series ofChad Rosier2011-11-171-11/+35
* Remove seemingly unnecessary duplicate VROUND definitions.Craig Topper2011-11-171-80/+4
* Add support for custom names for library functions in TargetLibraryInfo. Add...Eli Friedman2011-11-173-13/+50
* Don't unconditionally set the kill flag.Chad Rosier2011-11-171-1/+1
* Turn on vzeroupper insertion on call boundaries for AVX; it works as far as I...Eli Friedman2011-11-171-1/+1
* Make sure to replace the chain properly when DAGCombining a LOAD+EXTRACT_VECT...Eli Friedman2011-11-161-4/+17
* Object/COFF: Support common symbols.Michael J. Spencer2011-11-161-1/+3
* Generalize the fixup info for ARM mode.Jim Grosbach2011-11-161-2/+2
* Lower 64-bit constant pool node.Akira Hatanaka2011-11-161-8/+12
* Lower 64-bit block address.Akira Hatanaka2011-11-161-9/+11
* Fix encoding of NOP used for padding in ARM mode .align.Jim Grosbach2011-11-161-1/+1
* Add patterns for 64-bit tglobaladdr, tblockaddress, tjumptable and tconstpoolAkira Hatanaka2011-11-162-7/+24
* 64-bit jump register instruction.Akira Hatanaka2011-11-162-6/+7
* Another missing X86ISD::MOVLPD pattern. rdar://10450317Evan Cheng2011-11-161-0/+2
* ARM assembly parsing for shifted register operands for MOV instruction.Jim Grosbach2011-11-161-0/+2
* Clean up debug printing of ARM shifted operands.Jim Grosbach2011-11-161-9/+6
* Add fast-isel stats to determine who's doing all the work, the Chad Rosier2011-11-161-0/+7
* Fix the stats collection for fast-isel. The failed count was only accountingChad Rosier2011-11-161-5/+18
* ARM assmebly two operand forms for LSR, ASR, LSL, ROR register.Jim Grosbach2011-11-161-0/+12
* ARM assembly parsing for RRX mnemonic.Jim Grosbach2011-11-162-1/+16
* Added missing comment about new custom lowering of DEC64Pete Cooper2011-11-161-0/+12
* Disable expensive two-address optimizations at -O0. rdar://10453055Evan Cheng2011-11-161-0/+8
* Check to make sure we can select the instruction before trying to put theChad Rosier2011-11-161-6/+6
* Disable the assertion again. Looks like fastisel is still generating bad kill...Evan Cheng2011-11-161-1/+2
* ARM mode aliases for bitwise instructions w/ register operands.Jim Grosbach2011-11-162-0/+38
* Fix tablegen warning: hasSideEffects is inferred for eh_sjlj_dispatchsetup.Bob Wilson2011-11-161-1/+1
* lib/Target/ARM/CMakeLists.txt: Disable optimization in ARMISelLowering.cpp al...NAKAMURA Takumi2011-11-161-2/+2
* Sink codegen optimization level into MCCodeGenInfo along side relocation modelEvan Cheng2011-11-1640-253/+277
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