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* Add FIXME.Jim Grosbach2010-11-051-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118280 91177308-0d34-0410-b5e6-96231b3b80d8
* When passing a parameter using the 'byval' mechanism, inline code needs to ↵Duncan Sands2010-11-051-0/+2
| | | | | | | | | | | | | | be used to perform the copy, which may be of lots of memory [*]. It would be good if the fall-back code generated something reasonable, i.e. did the copy in a loop, rather than vast numbers of loads and stores. Add a note about this. Currently target specific code seems to always kick in so this is more of a theoretical issue rather than a practical one now that X86 has been fixed. [*] It's amazing how often people pass mega-byte long arrays by copy... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118275 91177308-0d34-0410-b5e6-96231b3b80d8
* CrashRecoveryContext: Add RunSafelyOnThread helper function.Daniel Dunbar2010-11-051-0/+23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118272 91177308-0d34-0410-b5e6-96231b3b80d8
* When passing a huge parameter using the byval mechanism, a longDuncan Sands2010-11-041-7/+17
| | | | | | | | | | sequence of loads and stores was being generated to perform the copy on the x86 targets if the parameter was less than 4 byte aligned, causing llc to use up vast amounts of memory and time. Use a "rep movs" form instead. PR7170. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118260 91177308-0d34-0410-b5e6-96231b3b80d8
* Use arrays instead of constant-sized SmallVectors.Benjamin Kramer2010-11-041-132/+143
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118257 91177308-0d34-0410-b5e6-96231b3b80d8
* Add 118023 back, but with proper spelling for .uleb128/.sleb128.Rafael Espindola2010-11-042-9/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118254 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert previous patch. Some targets don't support uleb and sayRafael Espindola2010-11-041-6/+7
| | | | | | they do :-( git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118250 91177308-0d34-0410-b5e6-96231b3b80d8
* MCize.Rafael Espindola2010-11-041-7/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118249 91177308-0d34-0410-b5e6-96231b3b80d8
* Introduce DIBuilder. It is intended to be a front-end friendly interface to ↵Devang Patel2010-11-042-0/+250
| | | | | | | | | | | | | | | emit debuggging information entries in LLVM IR. To create debugging information for a pointer, using DIBUilder front-end just needs DBuilder.CreatePointerType(Ty, Size); instead of DebugFactory.CreateDerivedType(llvm::dwarf::DW_TAG_pointer_type, TheCU, "", getOrCreateMainFile(), 0, Size, 0, 0, 0, OCTy); git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118248 91177308-0d34-0410-b5e6-96231b3b80d8
* In the calling convention logic, ValVT is always a legal type,Duncan Sands2010-11-047-22/+22
| | | | | | | | and as such can be represented by an MVT - the more complicated EVT is not needed. Use MVT for ValVT everywhere. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118245 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix @llvm.prefetch isel. Selecting between pld / pldw using the first ↵Evan Cheng2010-11-043-38/+37
| | | | | | immediate rw. There is currently no intrinsic that matches to pli. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118237 91177308-0d34-0410-b5e6-96231b3b80d8
* System: Add llvm_execute_on_thread, which does what it says.Daniel Dunbar2010-11-041-0/+52
| | | | | | | - Primarily useful for running some code with a specified stack size, when pthreads are available. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118222 91177308-0d34-0410-b5e6-96231b3b80d8
* Add ARM fixup info for load/store label references. Probably will need a bit ofJim Grosbach2010-11-042-30/+79
| | | | | | | tweaking when we start using it for object file emission or JIT, but it's a start. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118221 91177308-0d34-0410-b5e6-96231b3b80d8
* Add encoding for VSTR.Bill Wendling2010-11-042-30/+30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118220 91177308-0d34-0410-b5e6-96231b3b80d8
* Disable fancy splitting during spilling unless -extra-spiller-splits is given.Jakob Stoklund Olesen2010-11-041-8/+18
| | | | | | | | This way, InlineSpiller does the same amount of splitting as the standard spiller. Splitting should really be guided by the register allocator, and doesn't belong in the spiller at all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118216 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach ARM Target to use the tblgen support for generating an MC'izedJim Grosbach2010-11-033-47/+64
| | | | | | CodeEmitter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118209 91177308-0d34-0410-b5e6-96231b3b80d8
* Covert VORRIMM to be produced via early target-specific DAG combining, ↵Owen Anderson2010-11-031-31/+26
| | | | | | | | | rather than legalization. This is both the conceptually correct place for it, as well as allowing it to be more aggressive. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118204 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for code generation of the one register with immediate form of vorr.Owen Anderson2010-11-033-1/+74
| | | | | | | | We could be more aggressive about making this work for a larger range of constants, but this seems like a good start. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118201 91177308-0d34-0410-b5e6-96231b3b80d8
* trailing whitespaceJim Grosbach2010-11-031-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118199 91177308-0d34-0410-b5e6-96231b3b80d8
* Just return undef for invalid masks or elts, and since we're doing that,Eric Christopher2010-11-031-5/+6
| | | | | | | just do it earlier too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118195 91177308-0d34-0410-b5e6-96231b3b80d8
* Let RegAllocBasic require MachineDominators - they are already available andJakob Stoklund Olesen2010-11-031-0/+3
| | | | | | splitting needs them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118194 91177308-0d34-0410-b5e6-96231b3b80d8
* Tag debug output as regallocJakob Stoklund Olesen2010-11-032-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118193 91177308-0d34-0410-b5e6-96231b3b80d8
* Optimize generated code for integer materialization a bit.Eric Christopher2010-11-031-1/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118192 91177308-0d34-0410-b5e6-96231b3b80d8
* Unlike a lot of NEON instructions, vext isn't _actually_ parameterized by ↵Owen Anderson2010-11-031-9/+31
| | | | | | | | | | element size. Instead, all of the different element sizes are pseudo instructions that map down to vext.8 underneath, with the immediate shifted left to reflect the increased element size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118183 91177308-0d34-0410-b5e6-96231b3b80d8
* Add codegen patterns for VST1-lane instructions. Radar 8599955.Bob Wilson2010-11-031-8/+17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118176 91177308-0d34-0410-b5e6-96231b3b80d8
* Check for extractelement with a variable operand for the element number.Bob Wilson2010-11-031-10/+15
| | | | | | For NEON we had been assuming this was always an immediate constant. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118175 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename FindExecutable to PrependMainExecutablePath.Mikhail Glushenkov2010-11-032-8/+10
| | | | | | Makes it more clear that it is just a path manipulation function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118174 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename PointsToLocalMemory to PointsToLocalOrConstantMemory to makeDuncan Sands2010-11-031-8/+11
| | | | | | | the code more self-documenting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118171 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify uses of MVT and EVT. An MVT can be compared directlyDuncan Sands2010-11-037-20/+16
| | | | | | | | with a SimpleValueType, while an EVT supports equality and inequality comparisons with SimpleValueType. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118169 91177308-0d34-0410-b5e6-96231b3b80d8
* Inside the calling convention logic LocVT is always a simpleDuncan Sands2010-11-0312-100/+101
| | | | | | | | | | | value type, so there is no point in passing it around using an EVT. Use the simpler MVT everywhere. Rather than trying to propagate this information maximally in all the code that using the calling convention stuff, I chose to do a mainly low impact change instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118167 91177308-0d34-0410-b5e6-96231b3b80d8
* If we have an undef mask our Elt will be -1 for our access, handleEric Christopher2010-11-031-3/+7
| | | | | | | | | this by using an undef as a pointer. Fixes rdar://8625016 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118164 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix preload instruction isel. Only v7 supports pli, and only v7 with mp ↵Evan Cheng2010-11-0310-36/+83
| | | | | | extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118160 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536.Evan Cheng2010-11-035-47/+47
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118152 91177308-0d34-0410-b5e6-96231b3b80d8
* Put the PC encoding in the correct bit position.Bill Wendling2010-11-031-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118151 91177308-0d34-0410-b5e6-96231b3b80d8
* Invert these branches by default, it makes assembly comparisons a littleEric Christopher2010-11-031-2/+2
| | | | | | | easier to read. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118148 91177308-0d34-0410-b5e6-96231b3b80d8
* The MC code couldn't handle ARM LDR instructions with negative offsets:Bill Wendling2010-11-036-52/+140
| | | | | | | | | | | | | vldr.64 d1, [r0, #-32] The problem was with how the addressing mode 5 encodes the offsets. This change makes sure that the way offsets are handled in addressing mode 5 is consistent throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue" method into an "Imm12" and "addressing mode 5" version. But not to worry! The majority of the duplicated code has been unified. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118144 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix DAGCombiner to avoid going into an infinite loop when itDan Gohman2010-11-031-1/+36
| | | | | | | | encounters (and:i64 (shl:i64 (load:i64), 1), 0xffffffff). This fixes rdar://8606584. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118143 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused function.Jim Grosbach2010-11-032-9/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118141 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the no longer used 'Modifier' optional operand to the ARMJim Grosbach2010-11-032-17/+8
| | | | | | printOperand() asm printer helper functions. rdar://8425198 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118140 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused function.Jim Grosbach2010-11-032-12/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118139 91177308-0d34-0410-b5e6-96231b3b80d8
* Break ARM addrmode4 (load/store multiple base address) into its constituentJim Grosbach2010-11-039-104/+90
| | | | | | | parts. Represent the operation mode as an optional operand instead. rdar://8614429 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118137 91177308-0d34-0410-b5e6-96231b3b80d8
* Two sets of changes. Sorry they are intermingled.Evan Cheng2010-11-039-110/+155
| | | | | | | | | | | | | | 1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to "optimize for latency". Call instructions don't have the right latency and this is more likely to use introduce spills. 2. Fix if-converter cost function. For ARM, it should use instruction latencies, not # of micro-ops since multi-latency instructions is completely executed even when the predicate is false. Also, some instruction will be "slower" when they are predicated due to the register def becoming implicit input. rdar://8598427 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118135 91177308-0d34-0410-b5e6-96231b3b80d8
* Modify scheduling itineraries to correct instruction latencies (not operandEvan Cheng2010-11-032-314/+314
| | | | | | | latencies) of loads. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118134 91177308-0d34-0410-b5e6-96231b3b80d8
* Print an error as one big string instead of breaking it up.Dan Gohman2010-11-031-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118130 91177308-0d34-0410-b5e6-96231b3b80d8
* Delete unused variables.Dan Gohman2010-11-031-3/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118128 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove several unhelpful checks for isValid from sys::Path.Dan Gohman2010-11-031-26/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118127 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure we're only storing a single bit here.Eric Christopher2010-11-021-2/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118126 91177308-0d34-0410-b5e6-96231b3b80d8
* per a suggestion by Frits van Bommel, mark all MBlaze Pseudo Chris Lattner2010-11-023-5/+8
| | | | | | | | instructions as isCodeGenOnly in the parent class instead of sprinkling it throughout the .td files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118125 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r118097 to fix buildbots.Owen Anderson2010-11-022-203/+203
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118121 91177308-0d34-0410-b5e6-96231b3b80d8
* Completely reject instructions that have an operand in theirChris Lattner2010-11-022-38/+48
| | | | | | | | | | | | | | ins/outs list that isn't specified by their asmstring. Previously the asmmatcher would just force a 0 register into it, which clearly isn't right. Mark a bunch of ARM instructions that use this as isCodeGenOnly. Some of them are clearly pseudo instructions (like t2TBB) others use a weird hasExtraSrcRegAllocReq thing that will either need to be removed or the asmmatcher will need to be taught about it (someday). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118119 91177308-0d34-0410-b5e6-96231b3b80d8
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