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test
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CodeGen
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ARM
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reg_sequence.ll
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Author
Age
Files
Lines
*
Replace some NEON vmovl intrinsic that I missed earlier.
Bob Wilson
2010-08-20
1
-4
/
+2
*
Use a target-specific VMOVIMM DAG node instead of BUILD_VECTOR to represent
Bob Wilson
2010-07-13
1
-1
/
+1
*
Print "dregpair" NEON operands with a space between them, for readability and
Bob Wilson
2010-07-09
1
-2
/
+2
*
Reenable DAG combining for vector shuffles. It looks like it was temporarily
Bob Wilson
2010-07-09
1
-1
/
+0
*
Eliminate the other half of the BRCOND optimization, and update
Dan Gohman
2010-06-24
1
-2
/
+2
*
Remove arm_apcscc from the test files. It is the default and doing this
Rafael Espindola
2010-06-17
1
-4
/
+4
*
Fix some latency computation bugs: if the use is not a machine opcode do not ...
Evan Cheng
2010-05-28
1
-3
/
+4
*
Change ARM scheduling default to list-hybrid if the target supports floating ...
Evan Cheng
2010-05-21
1
-6
/
+6
*
TwoAddressInstructionPass doesn't really know how to merge live intervals when
Jakob Stoklund Olesen
2010-05-19
1
-0
/
+17
*
Fix PR7162: Use source register classes and sub-indices to determine the corr...
Evan Cheng
2010-05-18
1
-0
/
+38
*
Fix PR7175. Insert copies of a REG_SEQUENCE source if it is used by other REG...
Evan Cheng
2010-05-17
1
-0
/
+35
*
Fix PR7156. If the sources of a REG_SEQUENCE are all IMPLICIT_DEF's. Replace ...
Evan Cheng
2010-05-17
1
-0
/
+46
*
Careful with reg_sequence coalescing to not to overwrite sub-register indices.
Evan Cheng
2010-05-17
1
-0
/
+42
*
Turn on -neon-reg-sequence by default.
Evan Cheng
2010-05-17
1
-0
/
+170