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* Replace some NEON vmovl intrinsic that I missed earlier.Bob Wilson2010-08-201-4/+2
* Use a target-specific VMOVIMM DAG node instead of BUILD_VECTOR to representBob Wilson2010-07-131-1/+1
* Print "dregpair" NEON operands with a space between them, for readability andBob Wilson2010-07-091-2/+2
* Reenable DAG combining for vector shuffles. It looks like it was temporarilyBob Wilson2010-07-091-1/+0
* Eliminate the other half of the BRCOND optimization, and updateDan Gohman2010-06-241-2/+2
* Remove arm_apcscc from the test files. It is the default and doing thisRafael Espindola2010-06-171-4/+4
* Fix some latency computation bugs: if the use is not a machine opcode do not ...Evan Cheng2010-05-281-3/+4
* Change ARM scheduling default to list-hybrid if the target supports floating ...Evan Cheng2010-05-211-6/+6
* TwoAddressInstructionPass doesn't really know how to merge live intervals whenJakob Stoklund Olesen2010-05-191-0/+17
* Fix PR7162: Use source register classes and sub-indices to determine the corr...Evan Cheng2010-05-181-0/+38
* Fix PR7175. Insert copies of a REG_SEQUENCE source if it is used by other REG...Evan Cheng2010-05-171-0/+35
* Fix PR7156. If the sources of a REG_SEQUENCE are all IMPLICIT_DEF's. Replace ...Evan Cheng2010-05-171-0/+46
* Careful with reg_sequence coalescing to not to overwrite sub-register indices.Evan Cheng2010-05-171-0/+42
* Turn on -neon-reg-sequence by default.Evan Cheng2010-05-171-0/+170