external_llvm.git - Unnamed repository; edit this file 'description' to name the repository.

	Commit message (Expand)	Author	Age	Files	Lines
*	Revert "Tests: Be less dependent on a specific schedule/regalloc"	Matthias Braun	2013-10-11	1	-2/+2
*	Tests: Be less dependent on a specific schedule/regalloc	Matthias Braun	2013-10-11	1	-2/+2
*	ARM: implement some simple f64 materializations.	Tim Northover	2013-08-20	1	-3/+2
*	Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to f...	Stephen Lin	2013-07-14	1	-10/+10
*	Make ARMAsmPrinter generate the correct alignment specifier syntax in instruc...	Kristof Beyls	2013-02-22	1	-2/+2
*	Enable the new coalescer algorithm by default.	Jakob Stoklund Olesen	2012-09-27	1	-1/+0
*	Try to make these tests more portable.	Evan Cheng	2012-09-20	1	-2/+2
*	Use vld1 / vst2 for unaligned v2f64 load / store. e.g. Use vld1.16 for 2-byte	Evan Cheng	2012-09-18	1	-3/+3
*	This commit contains a few changes that had to go in together.	Nadav Rotem	2012-04-01	1	-1/+1
*	ARM VLDR/VSTR instructions don't need a size suffix.	Jim Grosbach	2011-11-14	1	-2/+2
*	Simplify some uses of utohexstr.	Benjamin Kramer	2011-11-07	1	-1/+1
*	Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues ...	Owen Anderson	2011-07-15	1	-5/+5
*	Fix ARM tests to be register allocator independent.	Jakob Stoklund Olesen	2011-03-31	1	-10/+12
*	Making use of VFP / NEON floating point multiply-accumulate / subtraction is	Evan Cheng	2010-12-05	1	-1/+2
*	Two sets of changes. Sorry they are intermingled.	Evan Cheng	2010-11-03	1	-1/+0
*	putback r116983 and fix simple-fp-encoding.ll tests	Andrew Trick	2010-10-21	1	-1/+2
*	Revert r116983, which is breaking all the buildbots.	Owen Anderson	2010-10-21	1	-2/+1
*	Add missing scheduling itineraries for transfers between core registers and V...	Evan Cheng	2010-10-21	1	-1/+2
*	Correct some load / store instruction itinerary mistakes:	Evan Cheng	2010-10-09	1	-1/+1
*	Change register allocation order for ARM VFP and NEON registers to put the	Bob Wilson	2010-10-08	1	-17/+17
*	Convert VLD1 and VLD2 instructions to use pseudo-instructions until	Bob Wilson	2010-09-02	1	-1/+1
*	Add alignment arguments to all the NEON load/store intrinsics.	Bob Wilson	2010-08-27	1	-32/+33
*	Replace some NEON vmovl intrinsic that I missed earlier.	Bob Wilson	2010-08-20	1	-4/+2
*	Use a target-specific VMOVIMM DAG node instead of BUILD_VECTOR to represent	Bob Wilson	2010-07-13	1	-1/+1
*	Print "dregpair" NEON operands with a space between them, for readability and	Bob Wilson	2010-07-09	1	-2/+2
*	Reenable DAG combining for vector shuffles. It looks like it was temporarily	Bob Wilson	2010-07-09	1	-1/+0
*	Eliminate the other half of the BRCOND optimization, and update	Dan Gohman	2010-06-24	1	-2/+2
*	Remove arm_apcscc from the test files. It is the default and doing this	Rafael Espindola	2010-06-17	1	-4/+4
*	Fix some latency computation bugs: if the use is not a machine opcode do not ...	Evan Cheng	2010-05-28	1	-3/+4
*	Change ARM scheduling default to list-hybrid if the target supports floating ...	Evan Cheng	2010-05-21	1	-6/+6
*	TwoAddressInstructionPass doesn't really know how to merge live intervals when	Jakob Stoklund Olesen	2010-05-19	1	-0/+17
*	Fix PR7162: Use source register classes and sub-indices to determine the corr...	Evan Cheng	2010-05-18	1	-0/+38
*	Fix PR7175. Insert copies of a REG_SEQUENCE source if it is used by other REG...	Evan Cheng	2010-05-17	1	-0/+35
*	Fix PR7156. If the sources of a REG_SEQUENCE are all IMPLICIT_DEF's. Replace ...	Evan Cheng	2010-05-17	1	-0/+46
*	Careful with reg_sequence coalescing to not to overwrite sub-register indices.	Evan Cheng	2010-05-17	1	-0/+42
*	Turn on -neon-reg-sequence by default.	Evan Cheng	2010-05-17	1	-0/+170