aboutsummaryrefslogtreecommitdiffstats
path: root/test/CodeGen/ARM/reg_sequence.ll
Commit message (Expand)AuthorAgeFilesLines
* Update aosp/master llvm for rebase to r233350Pirama Arumuga Nainar2015-04-091-13/+13
* Update LLVM for rebase to r212749.Stephen Hines2014-07-211-2/+2
* Update to LLVM 3.5a.Stephen Hines2014-04-241-3/+5
* Revert "Tests: Be less dependent on a specific schedule/regalloc"Matthias Braun2013-10-111-2/+2
* Tests: Be less dependent on a specific schedule/regallocMatthias Braun2013-10-111-2/+2
* ARM: implement some simple f64 materializations.Tim Northover2013-08-201-3/+2
* Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to f...Stephen Lin2013-07-141-10/+10
* Make ARMAsmPrinter generate the correct alignment specifier syntax in instruc...Kristof Beyls2013-02-221-2/+2
* Enable the new coalescer algorithm by default.Jakob Stoklund Olesen2012-09-271-1/+0
* Try to make these tests more portable.Evan Cheng2012-09-201-2/+2
* Use vld1 / vst2 for unaligned v2f64 load / store. e.g. Use vld1.16 for 2-byteEvan Cheng2012-09-181-3/+3
* This commit contains a few changes that had to go in together.Nadav Rotem2012-04-011-1/+1
* ARM VLDR/VSTR instructions don't need a size suffix.Jim Grosbach2011-11-141-2/+2
* Simplify some uses of utohexstr.Benjamin Kramer2011-11-071-1/+1
* Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues ...Owen Anderson2011-07-151-5/+5
* Fix ARM tests to be register allocator independent.Jakob Stoklund Olesen2011-03-311-10/+12
* Making use of VFP / NEON floating point multiply-accumulate / subtraction isEvan Cheng2010-12-051-1/+2
* Two sets of changes. Sorry they are intermingled.Evan Cheng2010-11-031-1/+0
* putback r116983 and fix simple-fp-encoding.ll testsAndrew Trick2010-10-211-1/+2
* Revert r116983, which is breaking all the buildbots.Owen Anderson2010-10-211-2/+1
* Add missing scheduling itineraries for transfers between core registers and V...Evan Cheng2010-10-211-1/+2
* Correct some load / store instruction itinerary mistakes:Evan Cheng2010-10-091-1/+1
* Change register allocation order for ARM VFP and NEON registers to put theBob Wilson2010-10-081-17/+17
* Convert VLD1 and VLD2 instructions to use pseudo-instructions untilBob Wilson2010-09-021-1/+1
* Add alignment arguments to all the NEON load/store intrinsics.Bob Wilson2010-08-271-32/+33
* Replace some NEON vmovl intrinsic that I missed earlier.Bob Wilson2010-08-201-4/+2
* Use a target-specific VMOVIMM DAG node instead of BUILD_VECTOR to representBob Wilson2010-07-131-1/+1
* Print "dregpair" NEON operands with a space between them, for readability andBob Wilson2010-07-091-2/+2
* Reenable DAG combining for vector shuffles. It looks like it was temporarilyBob Wilson2010-07-091-1/+0
* Eliminate the other half of the BRCOND optimization, and updateDan Gohman2010-06-241-2/+2
* Remove arm_apcscc from the test files. It is the default and doing thisRafael Espindola2010-06-171-4/+4
* Fix some latency computation bugs: if the use is not a machine opcode do not ...Evan Cheng2010-05-281-3/+4
* Change ARM scheduling default to list-hybrid if the target supports floating ...Evan Cheng2010-05-211-6/+6
* TwoAddressInstructionPass doesn't really know how to merge live intervals whenJakob Stoklund Olesen2010-05-191-0/+17
* Fix PR7162: Use source register classes and sub-indices to determine the corr...Evan Cheng2010-05-181-0/+38
* Fix PR7175. Insert copies of a REG_SEQUENCE source if it is used by other REG...Evan Cheng2010-05-171-0/+35
* Fix PR7156. If the sources of a REG_SEQUENCE are all IMPLICIT_DEF's. Replace ...Evan Cheng2010-05-171-0/+46
* Careful with reg_sequence coalescing to not to overwrite sub-register indices.Evan Cheng2010-05-171-0/+42
* Turn on -neon-reg-sequence by default.Evan Cheng2010-05-171-0/+170
generated by cgit v1.1 at 2024-05-20 15:02:31 +0000