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* ARM: do not add a regmask for TAILJUMPsMatthias Braun2013-10-041-0/+35
| | | | | | | | | The jump doesn't really kill the registers, the following call does but we never get back anyway. This avoids some verify-machineinstrs problems when TAILJUMPs are if-converted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191962 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: preserve undef flag in pseudo instruction expandersMatthias Braun2013-10-041-0/+7
| | | | | | | Copy over the whole register machine operand instead of creating a new one with an incomplete set of flags. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191961 91177308-0d34-0410-b5e6-96231b3b80d8
* [arm] Enhance the test case by checking .fpu directive.Logan Chien2013-10-031-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191891 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: support interrupt attributeTim Northover2013-10-011-0/+130
| | | | | | | | | | | This function-attribute modifies the callee-saved register list and function epilogue (specifically the return instruction) so that a routine is suitable for use as an interrupt-handler of the specified type without disrupting user-mode applications. rdar://problem/14207019 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191766 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Introduce the 'sevl' instruction in ARMv8.Joey Gouly2013-10-011-0/+3
| | | | | | | | This also removes the restriction on the immediate field of the 'hint' instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191744 91177308-0d34-0410-b5e6-96231b3b80d8
* TBAA: remove !tbaa from testing cases when they are not needed.Manman Ren2013-09-303-43/+29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191689 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR 17372: Emitting PLD for stack address for ARM Thumb2Weiming Zhao2013-09-261-0/+22
| | | | | | | | t2PLDi12, t2PLDi8, t2PLDs was omitted in Thumb2InstrInfo. This patch fixes it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191441 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Use the load-acquire/store-release instructions optimally in AArch32.Amara Emerson2013-09-262-15/+1345
| | | | | | | Patch by Artyom Skrobov. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191428 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR 17368: disable vector mul distribution for square of add/sub for ARMWeiming Zhao2013-09-251-0/+11
| | | | | | | | | | | | | | | | | | | | | Generally, it is desirable to distribute (a + b) * c to a*c + b*c for ARM with VMLx forwarding, where a, b and c are vectors. However, for (a + b)*(a + b), distribution will result in one extra instruction. With distribution: x = a + b (add) y = a * x (mul) z = y + b * y (mla) Without distribution: x = a + b (add) z = x * x (mul) This patch checks if a mul is a square of add/sub. If yes, skip distribution. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191410 91177308-0d34-0410-b5e6-96231b3b80d8
* [PR16882] Ignore noreturn definitions when setting isPhysRegUsed.Quentin Colombet2013-09-251-0/+38
| | | | | | | | | | | | | | | | | | PEI inserts a save/restore sequence for the link register, according to the information it gets from the MachineRegisterInfo. MachineRegisterInfo is populated by the VirtRegMap pass. This pass was not aware of noreturn calls and was registering the definitions of these calls the same way as regular operations. Modify VirtRegPass so that it does not set the isPhysRegUsed information for registers only defined by noreturn calls. The rational is that a noreturn call is the "last instruction" of the program (if it returns the behavior is undefined), so everything that is defined by it cannot be used and will not interfere with anything else. Therefore, it is pointless to account for then. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191349 91177308-0d34-0410-b5e6-96231b3b80d8
* CriticalAntiDepBreaker is no longer needed for armv7 scheduling.Andrew Trick2013-09-253-5/+5
| | | | | | | | | | | | | | | | | This is being disabled because it is no longer needed for performance. It is only used by postRAscheduler which is also planned for removal, and it is implemented with an out-dated view of register liveness. It consideres aliases instead of register units, assumes valid kill flags, and assumes implicit uses on partial register defs. Kill flags and implicit operands are error prone and impossible to verify. We should gradually eliminate dependence on them in the postRA phases. Targets that still benefit from this should move to the MI scheduler. If that doesn't solve the problem, then we should add a hook to regalloc to optimize reload placement. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191348 91177308-0d34-0410-b5e6-96231b3b80d8
* Initialize BSSSection explicitly in InitMachOMCObjectFileInfo() to appease msvc.NAKAMURA Takumi2013-09-211-3/+0
| | | | | | This can revert r191087. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191128 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm/test: Mark 3 tests as XFAIL:msvc.NAKAMURA Takumi2013-09-201-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191087 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Add support for the v8 cryptography extensions.Amara Emerson2013-09-191-0/+57
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190996 91177308-0d34-0410-b5e6-96231b3b80d8
* [SelectionDAG] Teach the vector scalarizer about TRUNCATE.Quentin Colombet2013-09-171-0/+20
| | | | | | | | | | | | When a truncate node defines a legal vector type but uses an illegal vector type, the legalization process was splitting the vector until <1 x vector> type, but then it was failing to scalarize the node because it did not know how to handle TRUNCATE. <rdar://problem/14989896> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190830 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Change hasV8Fp to hasFPARMv8, and other command line optionsJoey Gouly2013-09-133-24/+24
| | | | | | | | to be more consistent. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190692 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Emit the proper .fpu directive.Joey Gouly2013-09-131-0/+7
| | | | | | | Patch by Bradley Smith! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190683 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Prevent generation of deprecated IT blocks on ARMv8 in Thumb mode.Joey Gouly2013-09-095-2/+53
| | | | | | | | | | IT blocks can only be one instruction lonf, and can only contain a subset of the 16 instructions. Patch by Artyom Skrobov! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190309 91177308-0d34-0410-b5e6-96231b3b80d8
* Debug Info Testing: update context from empty string to null.Manman Ren2013-09-081-1/+1
| | | | | | | Context should be either null or MDNode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190267 91177308-0d34-0410-b5e6-96231b3b80d8
* Debug Info Testing: updated to use NULL instead of "i32 0" in a few fields.Manman Ren2013-09-068-48/+48
| | | | | | | | | Field 2 of DIType (Context), field 9 of DIDerivedType (TypeDerivedFrom), field 12 of DICompositeType (ContainingType), fields 2, 7, 12 of DISubprogram (Context, Type, ContainingType). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190205 91177308-0d34-0410-b5e6-96231b3b80d8
* Debug Info Testing: Updated to use null instead of "i32 0" for containing-typeManman Ren2013-09-063-27/+27
| | | | | | | | | field of DICompositeType. This will help the follow-on patch of using DITypeRef for containing-type field. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190187 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Implement the new DMB/DSB operands.Joey Gouly2013-09-051-0/+16
| | | | | | | | | This removes the custom ISD Node: MEMBARRIER and replaces it with an intrinsic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190055 91177308-0d34-0410-b5e6-96231b3b80d8
* Reverting 190043 for now.Tilmann Scheller2013-09-051-76/+0
| | | | | | | | | Solution is not sufficient to prevent 'mov pc, lr' being emitted for jump table code. Test case doesn't trigger the added functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190047 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Add GPR register class excluding LR for use with the ADR instruction.Tilmann Scheller2013-09-051-0/+76
| | | | | | | | | | This improves code generation for jump tables by avoiding the emission of "mov pc, lr" which could fool the processor into believing this is a return from a function causing mispredicts. The code generation logic for jump tables uses ADR to materialize the address of the jump target. Patch by Daniel Stewart! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190043 91177308-0d34-0410-b5e6-96231b3b80d8
* Expand and rewrite comment.Eric Christopher2013-09-041-3/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189998 91177308-0d34-0410-b5e6-96231b3b80d8
* Change swift/vldm test case to be less dependent on allocation orderArnold Schwaighofer2013-09-041-16/+16
| | | | | | | 'Force' values in registers using the calling convention. Now, we only depend on the calling convention and that the allocator performs copy coalescing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189985 91177308-0d34-0410-b5e6-96231b3b80d8
* Swift: Only build vldm/vstm with q register aligned register listsArnold Schwaighofer2013-09-041-0/+28
| | | | | | | | Unaligned vldm/vstm need more uops and therefore are slower in general on swift. radar://14522102 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189961 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix scheduling for vldm/vstm instructions that load/store more than 32 bytes ↵Silviu Baranga2013-09-041-0/+71
| | | | | | on Cortex-A9. This also makes the existing code more compact. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189958 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Revert "ARM: Improve pattern for isel mul of vector by scalar.""Jim Grosbach2013-09-031-0/+18
| | | | | | | | | This reverts commit r189648. Fixes for the previously failing clang-side arm_neon_intrinsics test cases will be checked in separately. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189841 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Default to the Swift CPU when targeting armv7s/thumbv7s.Tilmann Scheller2013-09-021-1/+1
| | | | | | | | | | Test cases adjusted accordingly. This fixes rdar://14871821. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189766 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 189756 for now, it doesn't match what rdar://14871821 really wants.Tilmann Scheller2013-09-022-3/+3
| | | | | | | What we really want is to enable Swift by default for *v7s triples (and there already seems to be some logic which attempts to do that). In that case the iOS version doesn't matter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189763 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Default to Swift when compiling for iOS 6 or later.Tilmann Scheller2013-09-022-3/+3
| | | | | | | | | | Test cases adjusted accordingly. This fixes rdar://14871821. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189756 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "ARM: Improve pattern for isel mul of vector by scalar."Michael Gottesman2013-08-301-18/+0
| | | | | | | | This reverts commit r189619. The commit was breaking the arm_neon_intrinsic test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189648 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Improve pattern for isel mul of vector by scalar.Jim Grosbach2013-08-291-0/+18
| | | | | | | | | | | In addition to recognizing when the multiply's second argument is coming from an explicit VDUPLANE, also look for a plain scalar f32 reference and reference it via the corresponding vector lane. rdar://14870054 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189619 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: remove unused v(add|sub)hn and vqdml[as]l intrinsics.Tim Northover2013-08-283-144/+0
| | | | | | | Clang is now generating cleaner IR, so this removes the old variants which should be completely unused. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189481 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: add patterns for vqdmlal with separate vqdmull and vqaddsTim Northover2013-08-281-0/+90
| | | | | | | | | The vqdmlal and vqdmlls instructions are really just a fused pair consisting of a vqdmull.sN and a vqadd.sN. This adds patterns to LLVM so that we can switch Clang's CodeGen over to generating these instead of the special vqdmlal intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189480 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: add natural patterns for vaddhl and vsubhl.Tim Northover2013-08-272-0/+54
| | | | | | | | These instructions aren't particularly complicated and it's well worth having patterns for some reasonably useful LLVM IR that will match them. Soon we should be able to switch Clang over to producing this natural version. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189335 91177308-0d34-0410-b5e6-96231b3b80d8
* Debug Info: add an identifier field to DICompositeType.Manman Ren2013-08-2612-42/+42
| | | | | | | | | | | | | | | | | | | DICompositeType will have an identifier field at position 14. For now, the field is set to null in DIBuilder. For DICompositeTypes where the template argument field (the 13th field) was optional, modify DIBuilder to make sure the template argument field is set. Now DICompositeType has 15 fields. Update DIBuilder to use NULL instead of "i32 0" for null value of a MDNode. Update verifier to check that DICompositeType has 15 fields and the last field is null or a MDString. Update testing cases to include an extra field for DICompositeType. The identifier field will be used by type uniquing so a front end can genearte a DICompositeType with a unique identifer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189282 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Enable machine verifier for a few more tests.Jim Grosbach2013-08-262-3/+3
| | | | | | | | | Now that fast-isel is in better shape, we can enable the machine verifier for these tests, too. rdar://12594152 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189275 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Constrain regclass for TSTri instruction.Jim Grosbach2013-08-261-1/+1
| | | | | | | | | Get the register class right for the TST instruction. This keeps the machine verifier happy, enabling us to turn it on for another test. rdar://12594152 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189274 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: FastISel verifier error cleanup.Jim Grosbach2013-08-261-1/+1
| | | | | | | | | Constant pool and global value reference instructions need more restricted register classes than plain GPR. rdar://12594152 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189270 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Fix another ARM FastISel -verify-machineinstrs issue.Joey Gouly2013-08-231-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189109 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Add CodeGen for VMAXNM/VMINNM.Joey Gouly2013-08-231-0/+46
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189103 91177308-0d34-0410-b5e6-96231b3b80d8
* [stack protector] Work around an issue with the BMOVPCB_CALL instruction on ↵Michael Gottesman2013-08-221-0/+32
| | | | | | | | | | ARM by disabling does not return on __stack_chk_fail. This is to fix the bots while I look to see if there is something I can do here. rdar://14811848 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189076 91177308-0d34-0410-b5e6-96231b3b80d8
* Update to remove the no-frame-pointer-elim-non-leaf flag if it was set to ↵Bill Wendling2013-08-221-2/+2
| | | | | | 'false'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189068 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix some tests. The 'false' version just omits the attribute altogether.Bill Wendling2013-08-221-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189065 91177308-0d34-0410-b5e6-96231b3b80d8
* [Debug Info Tests] Update testing cases.Manman Ren2013-08-221-2/+1
| | | | | | | | | | A single metadata will not span multiple lines. This also helps me with my script to automatic update the testing cases. A debug info testing case should have a llvm.dbg.cu. Do not use hard-coded id for debug nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189033 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Add CodeGen support for VSEL.Joey Gouly2013-08-221-0/+309
| | | | | | | | | This uses the ARMcmov pattern that Tim cleaned up in r188995. Thanks to Simon Tatham for his floating point help! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189024 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Constrain some register classes in EmitAtomicBinary64 so thatJoey Gouly2013-08-222-2/+2
| | | | | | | we pass these tests with -verify-machineinstrs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189006 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix ARM FastISel PIC function call.Logan Chien2013-08-221-0/+23
| | | | | | | | The function call to external function should come with PLT relocation type if the PIC relocation model is used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189002 91177308-0d34-0410-b5e6-96231b3b80d8
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