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test
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CodeGen
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R600
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sub.ll
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Author
Age
Files
Lines
*
Update aosp/master LLVM for rebase to r230699.
Stephen Hines
2015-03-23
1
-18
/
+69
*
Update aosp/master LLVM for rebase to r222494.
Stephen Hines
2014-12-02
1
-14
/
+14
*
Update LLVM for rebase to r212749.
Stephen Hines
2014-07-21
1
-17
/
+33
*
Update LLVM for 3.5 rebase (r209712).
Stephen Hines
2014-05-29
1
-18
/
+37
*
R600/SI: Change formatting of printed registers.
Matt Arsenault
2013-11-12
1
-6
/
+6
*
R600/SI: Use -verify-machineinstrs for most tests
Tom Stellard
2013-10-10
1
-1
/
+1
*
R600: Non vector only instruction can be scheduled on trans unit
Vincent Lejeune
2013-09-04
1
-6
/
+6
*
R600: Set scheduling preference to Sched::Source
Tom Stellard
2013-08-12
1
-1
/
+1
*
R600: Add 64-bit float load/store support
Tom Stellard
2013-08-01
1
-1
/
+1
*
Revert "R600: Non vector only instruction can be scheduled on trans unit"
Tom Stellard
2013-07-31
1
-6
/
+6
*
R600: Non vector only instruction can be scheduled on trans unit
Vincent Lejeune
2013-07-31
1
-6
/
+6
*
R600/SI: Expand sub for v2i32 and v4i32 for SI
Tom Stellard
2013-06-20
1
-6
/
+31
*
R600: Expand SUB for v2i32/v4i32
Tom Stellard
2013-05-10
1
-0
/
+15