| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Swift: Only build vldm/vstm with q register aligned register lists | Arnold Schwaighofer | 2013-09-04 | 1 | -0/+28 |
| * | Fix scheduling for vldm/vstm instructions that load/store more than 32 bytes ... | Silviu Baranga | 2013-09-04 | 1 | -0/+71 |
| * | [Sparc] Fix an assertion failure while lowering fcmp on long double. | Venkatraman Govindaraju | 2013-09-04 | 1 | -0/+20 |
| * | Inplement aarch64 neon instructions in AdvSIMD(shift). About 24 shift instruc... | Hao Liu | 2013-09-04 | 1 | -0/+1524 |
| * | Revert "Revert "ARM: Improve pattern for isel mul of vector by scalar."" | Jim Grosbach | 2013-09-03 | 1 | -0/+18 |
| * | [SystemZ] Add support for TMHH, TMHL, TMLH and TMLL | Richard Sandiford | 2013-09-03 | 1 | -0/+352 |
| * | [Sparc] Add support for soft long double (fp128). | Venkatraman Govindaraju | 2013-09-03 | 1 | -19/+55 |
| * | [Sparc] Implement spill and load for long double(f128) registers. | Venkatraman Govindaraju | 2013-09-02 | 1 | -0/+15 |
| * | ARM: Default to the Swift CPU when targeting armv7s/thumbv7s. | Tilmann Scheller | 2013-09-02 | 1 | -1/+1 |
| * | Revert 189756 for now, it doesn't match what rdar://14871821 really wants. | Tilmann Scheller | 2013-09-02 | 2 | -3/+3 |
| * | ARM: Default to Swift when compiling for iOS 6 or later. | Tilmann Scheller | 2013-09-02 | 2 | -3/+3 |
| * | FileCheck-ize three tests of llvm/test/CodeGen/X86/h-register(s). | NAKAMURA Takumi | 2013-09-02 | 3 | -5/+56 |
| * | llvm/test/CodeGen/X86: Update tests with -mattr=-bmi not to take BMI, corresp... | NAKAMURA Takumi | 2013-09-02 | 5 | -7/+7 |
| * | Create BEXTR instructions for (and ((sra or srl) x, imm), (2**size - 1)). Fix... | Craig Topper | 2013-09-02 | 1 | -0/+25 |
| * | AVX-512: gather-scatter tests; added foldable instructions; | Elena Demikhovsky | 2013-09-02 | 1 | -14/+16 |
| * | AVX-512: Added GATHER and SCATTER instructions. | Elena Demikhovsky | 2013-09-01 | 1 | -0/+223 |
| * | Make sure we don't generate stubs for any of these functions because they | Reed Kotler | 2013-09-01 | 1 | -15/+13 |
| * | [PowerPC] Call support for fast-isel. | Bill Schmidt | 2013-08-30 | 2 | -0/+166 |
| * | Fix a problem with dual mips16/mips32 mode. When the underlying processor | Reed Kotler | 2013-08-30 | 1 | -0/+38 |
| * | [PowerPC] Add handling for conversions to fast-isel. | Bill Schmidt | 2013-08-30 | 1 | -0/+305 |
| * | Teach X86 backend to create BMI2 BZHI instructions from (and X, (add (shl 1, ... | Craig Topper | 2013-08-30 | 1 | -0/+45 |
| * | Revert "ARM: Improve pattern for isel mul of vector by scalar." | Michael Gottesman | 2013-08-30 | 1 | -18/+0 |
| * | mi-sched: improve the generic register pressure comparison. | Andrew Trick | 2013-08-30 | 3 | -17/+15 |
| * | mi-sched: Precompute a PressureDiff for each instruction, adjust for liveness... | Andrew Trick | 2013-08-30 | 3 | -4/+6 |
| * | [PowerPC] Handle selection of compare instructions in fast-isel. | Bill Schmidt | 2013-08-30 | 1 | -0/+289 |
| * | [PowerPC] Miscellaneous fast-isel test cases. | Bill Schmidt | 2013-08-30 | 4 | -0/+131 |
| * | [PowerPC] Add loads, stores, and related things to fast-isel. | Bill Schmidt | 2013-08-30 | 3 | -0/+434 |
| * | ARM: Improve pattern for isel mul of vector by scalar. | Jim Grosbach | 2013-08-29 | 1 | -0/+18 |
| * | AVX-512: added extend and truncate instructions. | Elena Demikhovsky | 2013-08-29 | 1 | -0/+127 |
| * | ARM: Use "dmb sy" for barriers on M-class CPUs | Tim Northover | 2013-08-28 | 1 | -1/+1 |
| * | ARM: remove unused v(add|sub)hn and vqdml[as]l intrinsics. | Tim Northover | 2013-08-28 | 3 | -144/+0 |
| * | ARM: add patterns for vqdmlal with separate vqdmull and vqadds | Tim Northover | 2013-08-28 | 1 | -0/+90 |
| * | [mips][msa] Added bnz.df, bnz.v, bz.df, and bz.v | Daniel Sanders | 2013-08-28 | 2 | -0/+134 |
| * | [mips][msa] Added load/store intrinsics. | Daniel Sanders | 2013-08-28 | 2 | -0/+298 |
| * | AVX-512: added SQRT, VRSQRT14, VCOMISS, VUCOMISS, VRCP14, VPABS | Elena Demikhovsky | 2013-08-28 | 3 | -0/+152 |
| * | [mips][msa] Added move.v | Daniel Sanders | 2013-08-28 | 1 | -0/+24 |
| * | [SystemZ] Add support for TMHH, TMHL, TMLH and TMLL | Richard Sandiford | 2013-08-28 | 3 | -2/+294 |
| * | [mips][msa] Added cfcmsa, and ctcmsa | Daniel Sanders | 2013-08-28 | 1 | -0/+167 |
| * | [mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ft... | Daniel Sanders | 2013-08-28 | 4 | -0/+976 |
| * | [mips][msa] Summarize tests | Daniel Sanders | 2013-08-28 | 40 | -4/+114 |
| * | [SystemZ] Extend memcmp support to all constant lengths | Richard Sandiford | 2013-08-28 | 2 | -4/+96 |
| * | Move some debug testcases to the debug info directory. | Eric Christopher | 2013-08-27 | 16 | -966/+0 |
| * | AVX-512: added conversion instructions. | Elena Demikhovsky | 2013-08-27 | 1 | -0/+186 |
| * | DAGCombiner: make sure or/shl/srl really has zero high bits before forming bswap | Tim Northover | 2013-08-27 | 1 | -6/+101 |
| * | ARM: add natural patterns for vaddhl and vsubhl. | Tim Northover | 2013-08-27 | 2 | -0/+54 |
| * | R600/SI: Enable local-memory-two-objects lit test | Michel Danzer | 2013-08-27 | 1 | -12/+17 |
| * | [mips][msa] Added tests for and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v ... | Daniel Sanders | 2013-08-27 | 1 | -43/+523 |
| * | [mips][msa] Added spill/reload support | Daniel Sanders | 2013-08-27 | 1 | -0/+597 |
| * | [SystemZ] Extend memcpy and memset support to all constant lengths | Richard Sandiford | 2013-08-27 | 5 | -29/+224 |
| * | [mips][msa] Added bitconverts for vector types for big and little-endian | Daniel Sanders | 2013-08-27 | 1 | -0/+1208 |
