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* R600/SI: Add more special cases for opcodes to ensureSRegLimit()Tom Stellard2013-08-066-45/+45
* Debug Info Finder|Verifier: handle DbgLoc attached to instructions.Manman Ren2013-08-064-7/+8
* Add PPC64 mulli patternHal Finkel2013-08-061-0/+16
* [NVPTX] Add missing patterns for i1 [s,u]int_to_fpJustin Holewinski2013-08-061-0/+37
* [NVPTX] Fix bug in stack code generation causes by MC conversionJustin Holewinski2013-08-061-0/+18
* [NVPTX] Start conversion to MC infrastructureJustin Holewinski2013-08-061-0/+18
* ARM: implement allowTruncateForTailCallTim Northover2013-08-061-0/+111
* Refactor isInTailCallPosition handlingTim Northover2013-08-063-0/+157
* Factor FlattenCFG out from SimplifyCFGTom Stellard2013-08-062-0/+115
* R600/SI: Add missing test for r187749Tom Stellard2013-08-051-0/+48
* [SystemZ] Use BRCT and BRCTG to eliminate add-&-compare sequencesRichard Sandiford2013-08-053-1/+237
* [SystemZ] Use LOAD AND TEST to eliminate comparisons against zeroRichard Sandiford2013-08-051-0/+223
* AVX-512 set: added mask operations, lowering BUILD_VECTOR for i1 vector types.Elena Demikhovsky2013-08-051-0/+58
* Add the saving of S2. This is needed for some of the floating pointReed Kotler2013-08-045-16/+17
* X86: Turn fp selects into mask operations.Benjamin Kramer2013-08-043-48/+290
* AVX-512 set: added VEXTRACTPS instructionElena Demikhovsky2013-08-041-1/+20
* X86: specify CPU on new test to fix atom buildbotTim Northover2013-08-041-1/+1
* X86: correct tail return address calculationTim Northover2013-08-041-0/+19
* Clean up code for Mips16 large frame handling.Reed Kotler2013-08-041-12/+25
* Fix PPC64 64-bit GPR inline asm constraint matchingHal Finkel2013-08-031-0/+65
* [mips] Expand vector truncating stores and extending loads.Akira Hatanaka2013-08-021-0/+11
* Temporarily revert "Debug Info Finder|Verifier: handle DbgLoc attached toEric Christopher2013-08-024-8/+7
* Use function attributes to indicate that we don't want to realign the stack.Bill Wendling2013-08-014-25/+702
* Fix some issues with Mips16 floating when certain intrinsics are present.Reed Kotler2013-08-011-0/+368
* Debug Info Finder|Verifier: handle DbgLoc attached to instructions.Manman Ren2013-08-014-7/+8
* R600: Add 64-bit float load/store supportTom Stellard2013-08-0115-43/+161
* R600: Use 64-bit alignment for 64-bit kernel argumentsTom Stellard2013-08-011-0/+2
* R600/SI: Custom lower i64 ZERO_EXTENDTom Stellard2013-08-011-0/+18
* [SystemZ] Reuse CC results for integer comparisons with zeroRichard Sandiford2013-08-012-0/+691
* [SystemZ] Prefer comparisons with zeroRichard Sandiford2013-08-015-10/+54
* AArch64: add initial NEON supportTim Northover2013-08-0123-1/+6098
* XCore target: Fix Vararg handlingRobert Lytton2013-08-012-17/+55
* XCore target: Add byval handlingRobert Lytton2013-08-011-0/+58
* Xcore targetRobert Lytton2013-08-011-0/+4
* Fix some misc. issues with Mips16 fp stubs.Reed Kotler2013-08-011-48/+50
* Revert "R600: Non vector only instruction can be scheduled on trans unit"Tom Stellard2013-07-3125-185/+73
* R600: Avoid more than 4 literals in the same instruction group at schedulingVincent Lejeune2013-07-311-0/+68
* R600: Non vector only instruction can be scheduled on trans unitVincent Lejeune2013-07-3125-73/+185
* [SystemZ] Implement isLegalAddressingMode()Richard Sandiford2013-07-311-0/+25
* [SystemZ] Be more careful about inverting CC masks (conditional loads)Richard Sandiford2013-07-312-14/+14
* [SystemZ] Be more careful about inverting CC masksRichard Sandiford2013-07-3147-124/+149
* [SystemZ] Move compare-and-branch generation even laterRichard Sandiford2013-07-311-0/+45
* [SystemZ] Postpone NI->RISBG conversion to convertToThreeAddress()Richard Sandiford2013-07-3129-431/+446
* Added INSERT and EXTRACT intructions from AVX-512 ISA.Elena Demikhovsky2013-07-311-0/+44
* Changed register names (and pointer keywords) to be lower case when using Int...Craig Topper2013-07-316-18/+18
* This test may have been sensitive to the ARM ABI...Andrew Trick2013-07-301-1/+1
* MI Sched fix: assert "Disconnected LRG within the scheduling region."Andrew Trick2013-07-301-1/+54
* R600/SI: Expand vector fp <-> int conversionsTom Stellard2013-07-304-36/+36
* [ARM] check bitwidth in PerformORCombineSaleem Abdulrasool2013-07-301-0/+32
* [R600] Replicate old DAGCombiner behavior in target specific DAG combine.Quentin Colombet2013-07-301-1/+0
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