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* [ARMv8] Prevent generation of deprecated IT blocks on ARMv8 in Thumb mode.Joey Gouly2013-09-0910-2/+289
* XCore handling of thread local loweringRobert Lytton2013-09-091-16/+55
* XCore target: change to Sched::SourceRobert Lytton2013-09-091-0/+25
* XCore target: fix weak linkage attribute handlingRobert Lytton2013-09-091-0/+17
* Generate compact unwind encoding from CFI directives.Bill Wendling2013-09-092-11/+15
* Implement aarch64 neon instruction set AdvSIMD (3V Diff), covering the follow...Jiangning Liu2013-09-091-0/+1806
* Debug Info Testing: use null instead of an empty string in context field.Manman Ren2013-09-091-1/+1
* Debug Info Testing: update context from empty string to null.Manman Ren2013-09-081-1/+1
* [mips] Fix typos.Akira Hatanaka2013-09-071-2/+2
* [mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index doubleAkira Hatanaka2013-09-071-15/+63
* [mips] Set instruction itineraries of loads, stores and conditional moves.Akira Hatanaka2013-09-061-16/+17
* Debug Info Testing: updated to use NULL instead of "i32 0" in a few fields.Manman Ren2013-09-0616-65/+65
* R600: Add support for LDS atomic subtractAaron Watry2013-09-061-0/+23
* Debug Info Testing: Updated to use null instead of "i32 0" for containing-typeManman Ren2013-09-063-27/+27
* SelectionDAG: create correct BooleanContent constantsTim Northover2013-09-061-0/+61
* [SystemZ] Tweak integer comparison codeRichard Sandiford2013-09-061-0/+101
* [SystemZ] Use XC for a memset of 0Richard Sandiford2013-09-061-42/+26
* Teach CodeGenPrepare about address spacesMatt Arsenault2013-09-061-0/+30
* [X86] Perform VSELECT DAG combines also before DAG type legalization.Juergen Ributzka2013-09-051-2/+1
* R600: Fix i64 to i32 trunc on SIMatt Arsenault2013-09-051-0/+19
* R600: Add support for local memory atomic addTom Stellard2013-09-051-0/+23
* R600: Expand SELECT nodes rather than custom lowering themTom Stellard2013-09-051-0/+46
* R600: Fix incorrect LDS size calculationTom Stellard2013-09-051-0/+26
* R600/SI: Don't emit S_WQM_B64 instruction for compute shadersTom Stellard2013-09-052-0/+14
* [ARMv8] Implement the new DMB/DSB operands.Joey Gouly2013-09-051-0/+16
* Reverting 190043 for now.Tilmann Scheller2013-09-051-76/+0
* ARM: Add GPR register class excluding LR for use with the ADR instruction.Tilmann Scheller2013-09-051-0/+76
* [SystemZ] Add NC, OC and XCRichard Sandiford2013-09-053-0/+511
* [Sparc] Correctly handle call to functions with ReturnsTwice attribute.Venkatraman Govindaraju2013-09-051-0/+70
* mi-sched: Force bottom up scheduling for generic targets.Andrew Trick2013-09-042-16/+11
* Expand and rewrite comment.Eric Christopher2013-09-041-3/+4
* Change swift/vldm test case to be less dependent on allocation orderArnold Schwaighofer2013-09-041-16/+16
* R600: Use shared op optimization when checking cycle compatibilityVincent Lejeune2013-09-041-0/+38
* R600: Non vector only instruction can be scheduled on trans unitVincent Lejeune2013-09-0424-127/+239
* R600: Remove fmul.v4f32.ll test which is redundant with fmul.llVincent Lejeune2013-09-041-15/+0
* Swift: Only build vldm/vstm with q register aligned register listsArnold Schwaighofer2013-09-041-0/+28
* Fix scheduling for vldm/vstm instructions that load/store more than 32 bytes ...Silviu Baranga2013-09-041-0/+71
* [Sparc] Fix an assertion failure while lowering fcmp on long double.Venkatraman Govindaraju2013-09-041-0/+20
* Inplement aarch64 neon instructions in AdvSIMD(shift). About 24 shift instruc...Hao Liu2013-09-041-0/+1524
* Revert "Revert "ARM: Improve pattern for isel mul of vector by scalar.""Jim Grosbach2013-09-031-0/+18
* [SystemZ] Add support for TMHH, TMHL, TMLH and TMLLRichard Sandiford2013-09-031-0/+352
* [Sparc] Add support for soft long double (fp128).Venkatraman Govindaraju2013-09-031-19/+55
* [Sparc] Implement spill and load for long double(f128) registers.Venkatraman Govindaraju2013-09-021-0/+15
* ARM: Default to the Swift CPU when targeting armv7s/thumbv7s.Tilmann Scheller2013-09-021-1/+1
* Revert 189756 for now, it doesn't match what rdar://14871821 really wants.Tilmann Scheller2013-09-022-3/+3
* ARM: Default to Swift when compiling for iOS 6 or later.Tilmann Scheller2013-09-022-3/+3
* FileCheck-ize three tests of llvm/test/CodeGen/X86/h-register(s).NAKAMURA Takumi2013-09-023-5/+56
* llvm/test/CodeGen/X86: Update tests with -mattr=-bmi not to take BMI, corresp...NAKAMURA Takumi2013-09-025-7/+7
* Create BEXTR instructions for (and ((sra or srl) x, imm), (2**size - 1)). Fix...Craig Topper2013-09-021-0/+25
* AVX-512: gather-scatter tests; added foldable instructions;Elena Demikhovsky2013-09-021-14/+16
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