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* Debug Info Finder|Verifier: handle DbgLoc attached to instructions.Manman Ren2013-08-014-7/+8
* R600: Add 64-bit float load/store supportTom Stellard2013-08-0115-43/+161
* R600: Use 64-bit alignment for 64-bit kernel argumentsTom Stellard2013-08-011-0/+2
* R600/SI: Custom lower i64 ZERO_EXTENDTom Stellard2013-08-011-0/+18
* [SystemZ] Reuse CC results for integer comparisons with zeroRichard Sandiford2013-08-012-0/+691
* [SystemZ] Prefer comparisons with zeroRichard Sandiford2013-08-015-10/+54
* AArch64: add initial NEON supportTim Northover2013-08-0123-1/+6098
* XCore target: Fix Vararg handlingRobert Lytton2013-08-012-17/+55
* XCore target: Add byval handlingRobert Lytton2013-08-011-0/+58
* Xcore targetRobert Lytton2013-08-011-0/+4
* Fix some misc. issues with Mips16 fp stubs.Reed Kotler2013-08-011-48/+50
* Revert "R600: Non vector only instruction can be scheduled on trans unit"Tom Stellard2013-07-3125-185/+73
* R600: Avoid more than 4 literals in the same instruction group at schedulingVincent Lejeune2013-07-311-0/+68
* R600: Non vector only instruction can be scheduled on trans unitVincent Lejeune2013-07-3125-73/+185
* [SystemZ] Implement isLegalAddressingMode()Richard Sandiford2013-07-311-0/+25
* [SystemZ] Be more careful about inverting CC masks (conditional loads)Richard Sandiford2013-07-312-14/+14
* [SystemZ] Be more careful about inverting CC masksRichard Sandiford2013-07-3147-124/+149
* [SystemZ] Move compare-and-branch generation even laterRichard Sandiford2013-07-311-0/+45
* [SystemZ] Postpone NI->RISBG conversion to convertToThreeAddress()Richard Sandiford2013-07-3129-431/+446
* Added INSERT and EXTRACT intructions from AVX-512 ISA.Elena Demikhovsky2013-07-311-0/+44
* Changed register names (and pointer keywords) to be lower case when using Int...Craig Topper2013-07-316-18/+18
* This test may have been sensitive to the ARM ABI...Andrew Trick2013-07-301-1/+1
* MI Sched fix: assert "Disconnected LRG within the scheduling region."Andrew Trick2013-07-301-1/+54
* R600/SI: Expand vector fp <-> int conversionsTom Stellard2013-07-304-36/+36
* [ARM] check bitwidth in PerformORCombineSaleem Abdulrasool2013-07-301-0/+32
* [R600] Replicate old DAGCombiner behavior in target specific DAG combine.Quentin Colombet2013-07-301-1/+0
* [DAGCombiner] insert_vector_elt: Avoid building a vector twice.Quentin Colombet2013-07-307-26/+53
* Debug Info: enable verifier for testing cases.Manman Ren2013-07-293-3/+3
* Debug Info: update testing cases to pass verifier.Manman Ren2013-07-2915-45/+61
* Proper va_arg/va_copy lowering on win64Nico Rieck2013-07-291-0/+60
* Allow generation of vmla.f32 instructions when targeting Cortex-A15. The patc...Silviu Baranga2013-07-291-1/+25
* Debug Info Verifier: verify SPs in llvm.dbg.sp.Manman Ren2013-07-2715-61/+64
* next batch of -disable-debug-info-verifierRafael Espindola2013-07-262-2/+2
* [mips] Implement llvm.trap intrinsic.Akira Hatanaka2013-07-261-0/+11
* Debug Info Verifier: enable verification of DICompileUnit.Manman Ren2013-07-2625-59/+85
* [mips] Print instructions "beq", "bne" and "or" using assembler pseudoAkira Hatanaka2013-07-263-24/+24
* Add a target legalize hook for SplitVectorOperand (again)Justin Holewinski2013-07-262-0/+43
* Revert "Add a target legalize hook for SplitVectorOperand"Rafael Espindola2013-07-262-41/+0
* Add a target legalize hook for SplitVectorOperandJustin Holewinski2013-07-262-0/+41
* PPC32 va_list is an actual structure so va_copy needs to copy the wholeRoman Divacky2013-07-251-0/+24
* Debug Info: improve the verifier to check field types.Manman Ren2013-07-2514-97/+100
* Remove the mblaze backend from llvm.Rafael Espindola2013-07-2517-1410/+0
* Evict local live ranges if they can be reassigned.Andrew Trick2013-07-254-12/+6
* Allocate local registers in order for optimal coloring.Andrew Trick2013-07-2517-73/+68
* Current batch of -disable-debug-info-verifier.Rafael Espindola2013-07-257-9/+9
* AArch64: add llc-based tests for previous commit.Tim Northover2013-07-252-2/+15
* [SystemZ] Rework compare and branch supportRichard Sandiford2013-07-251-0/+22
* [SystemZ] Add LOCR and LOCGRRichard Sandiford2013-07-251-0/+25
* [SystemZ] Add LOC and LOCGRichard Sandiford2013-07-252-0/+260
* [SystemZ] Add STOC and STOCGRichard Sandiford2013-07-254-2/+312
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