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* Merging r195574:Bill Wendling2013-11-271-2/+0
| | | | | | | | | | | | ------------------------------------------------------------------------ r195574 | venkatra | 2013-11-24 10:41:49 -0800 (Sun, 24 Nov 2013) | 2 lines [SparcV9]: Do not emit .register directives for global registers that are clobbered by calls but not used in the function itself. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195868 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195573:Bill Wendling2013-11-271-6/+16
| | | | | | | | | | | | ------------------------------------------------------------------------ r195573 | venkatra | 2013-11-24 09:41:41 -0800 (Sun, 24 Nov 2013) | 2 lines [SparcV9] Enable custom lowering of DYNAMIC_STACKALLOC in sparc64. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195867 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195779:Bill Wendling2013-11-271-0/+10
| | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r195779 | hliao | 2013-11-26 12:31:31 -0800 (Tue, 26 Nov 2013) | 7 lines Fix PR18054 - Fix bug in (vsext (vzext x)) -> (vsext x) in SIGN_EXTEND_IN_REG lowering where we need to check whether x is a vector type (in-reg type) of i8, i16 or i32; otherwise, that optimization is not valid. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195821 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195424:Bill Wendling2013-11-262-0/+155
| | | | | | | | | | | | | | ------------------------------------------------------------------------ r195424 | haoliu | 2013-11-22 00:47:22 -0800 (Fri, 22 Nov 2013) | 4 lines Fix the bugs about AArch64 Load/Store vector types and bitcast between i64 and vector types. e.g. "%tmp = load <2 x i64>* %ptr" can't be selected. "%tmp = bitcast i64 %in to <2 x i32>" can't be selected. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195764 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195408:Bill Wendling2013-11-261-42/+42
| | | | | | | | | | | | ------------------------------------------------------------------------ r195408 | jiangning | 2013-11-21 18:45:13 -0800 (Thu, 21 Nov 2013) | 2 lines For AArch64 back-end instruction selection, lower Neon_Lowxxx with EXTRCT_SUBREG. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195762 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195713:Bill Wendling2013-11-261-0/+3
| | | | | | | | | | | ------------------------------------------------------------------------ r195713 | kevinqin | 2013-11-25 18:33:42 -0800 (Mon, 25 Nov 2013) | 1 line [AArch64]Implement 128 bit register copy with NEON. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195758 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195469:Bill Wendling2013-11-261-0/+31
| | | | | | | | | | | | | | ------------------------------------------------------------------------ r195469 | dsanders | 2013-11-22 07:47:18 -0800 (Fri, 22 Nov 2013) | 4 lines [mips][msa] Add test case that should have been added in r195456. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195744 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195444:Bill Wendling2013-11-261-0/+27
| | | | | | | | | | | | | | ------------------------------------------------------------------------ r195444 | dsanders | 2013-11-22 03:24:50 -0800 (Fri, 22 Nov 2013) | 4 lines [mips][msa] Float vector constants cannot use ldi.[wd] directly. Bitcast from the appropriate integer vector type. Fixes an instruction selection failure detected by llvm-stress. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195742 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195364:Bill Wendling2013-11-261-0/+33
| | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r195364 | dsanders | 2013-11-21 08:11:31 -0800 (Thu, 21 Nov 2013) | 12 lines [mips][msa] Fix a corner case in performORCombine() when combining nodes into VSELECT. Mask == ~InvMask asserts if the width of Mask and InvMask differ. The combine isn't valid (with two exceptions, see below) if the widths differ so test for this before testing Mask == ~InvMask. In the specific cases of Mask=~0 and InvMask=0, as well as Mask=0 and InvMask=~0, the combine is still valid. However, there are more appropriate combines that could be used in these cases such as folding x & 0 to 0, or x & ~0 to x. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195741 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195343:Bill Wendling2013-11-261-0/+141
| | | | | | | | | | | | | | | ------------------------------------------------------------------------ r195343 | dsanders | 2013-11-21 03:40:14 -0800 (Thu, 21 Nov 2013) | 5 lines [mips][msa/dsp] Only do DSP combines if DSP is enabled. Fixes a crash (null pointer dereferenced) when MSA is enabled. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195740 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195731:Richard Sandiford2013-11-261-0/+14
| | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r195731 | rsandifo | 2013-11-26 10:53:16 +0000 (Tue, 26 Nov 2013) | 7 lines [SystemZ] Fix incorrect use of RISBG for a zero-extended right shift We would wrongly transform the testcase into the equivalent of an AND with 1. The problem was that, when testing whether the shifted-in bits of the right shift were significant, we used the width of the final zero-extended result rather than the width of the shifted value. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195736 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195716:Bill Wendling2013-11-261-0/+14
| | | | | | | | | | | | | ------------------------------------------------------------------------ r195716 | kevinqin | 2013-11-25 19:26:47 -0800 (Mon, 25 Nov 2013) | 3 lines Refactored the implementation of AArch64 NEON instruction ZIP, UZP and TRN. Fix a bug when mixed use of vget_high_u8() and vuzp_u8(). ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195735 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195670:Bill Wendling2013-11-251-0/+31
| | | | | | | | | | | | | | | ------------------------------------------------------------------------ r195670 | void | 2013-11-25 10:05:22 -0800 (Mon, 25 Nov 2013) | 5 lines Unrevert r195599 with testcase fix. I'm not sure how it was checking for the wrong values... PR18023. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195672 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195636:Bill Wendling2013-11-251-29/+0
| | | | | | | | | | | | ------------------------------------------------------------------------ r195636 | aemerson | 2013-11-25 03:24:18 -0800 (Mon, 25 Nov 2013) | 2 lines Revert r195599 as it broke the builds. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195671 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195635:Daniel Sanders2013-11-251-0/+143
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r195635 | dsanders | 2013-11-25 11:14:43 +0000 (Mon, 25 Nov 2013) | 19 lines Fixed tryFoldToZero() for vector types that need expansion. Summary: Moved the requirement for SelectionDAG::getConstant() to return legally typed nodes slightly earlier. There were two optional DAGCombine passes that were missed out and were required to produce type-legal DAGs. Simplified a code-path in tryFoldToZero() to use SelectionDAG::getConstant(). This provides support for both promoted and expanded vector types whereas the previous code only supported promoted vector types. Fixes a "Type for zero vector elements is not legal" assertion detected by an llvm-stress generated test. Reviewers: resistor CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D2251 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195651 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195330:Bill Wendling2013-11-251-0/+80
| | | | | | | | | | | | | | | ------------------------------------------------------------------------ r195330 | apazos | 2013-11-21 00:16:15 -0800 (Thu, 21 Nov 2013) | 5 lines Implemented Neon scalar vdup_lane intrinsics. Fixed scalar dup alias and added test case. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195612 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195327:Bill Wendling2013-11-252-70/+37
| | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r195327 | apazos | 2013-11-20 23:37:04 -0800 (Wed, 20 Nov 2013) | 6 lines Implemented Neon scalar by element intrinsics. Intrinsics implemented: vqdmull_lane, vqdmulh_lane, vqrdmulh_lane, vqdmlal_lane, vqdmlsl_lane scalar Neon intrinsics. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195611 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195514:Bill Wendling2013-11-252-9/+577
| | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r195514 | tstellar | 2013-11-22 15:07:58 -0800 (Fri, 22 Nov 2013) | 6 lines R600/SI: Fixing handling of condition codes We were ignoring the ordered/onordered bits and also the signed/unsigned bits of condition codes when lowering the DAG to MachineInstrs. NOTE: This is a candidate for the 3.4 branch. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195609 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195491:Bill Wendling2013-11-251-0/+42
| | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r195491 | probinson | 2013-11-22 11:11:24 -0800 (Fri, 22 Nov 2013) | 11 lines Teach ISel not to optimize 'optnone' functions (revised). Improvements over r195317: - Set/restore EnableFastISel flag instead of just running FastISel within SelectAllBasicBlocks; the flag is checked in various places, and FastISel won't run properly if those places don't do the right thing. - Test looks for normal ISel versus FastISel behavior, and not something more subtle that doesn't work everywhere. Based on work by Andrea Di Biagio. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195604 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195476:Bill Wendling2013-11-251-0/+16
| | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r195476 | hliao | 2013-11-22 09:56:57 -0800 (Fri, 22 Nov 2013) | 6 lines Fix PR18014 - When simplifying the mask generation for BLEND, check whether that mask is also consumed by other non-BLEND insns. If true, skip that simplification. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195602 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195599:Bill Wendling2013-11-251-0/+29
| | | | | | | | | | | | | | ------------------------------------------------------------------------ r195599 | void | 2013-11-24 21:01:21 -0800 (Sun, 24 Nov 2013) | 4 lines Don't look past volatile loads. A volatile load should block us from trying to coalesce stores. PR18023 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195600 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195439:Bill Wendling2013-11-222-4/+6
| | | | | | | | | | | | | ------------------------------------------------------------------------ r195439 | kcc | 2013-11-22 02:30:39 -0800 (Fri, 22 Nov 2013) | 3 lines Revert r195318 as it causes miscompilation (PR18029) ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195478 91177308-0d34-0410-b5e6-96231b3b80d8
* Add file missing from r195474.Richard Sandiford2013-11-221-0/+49
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195475 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195473:Richard Sandiford2013-11-221-0/+1
| | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r195473 | rsandifo | 2013-11-22 17:28:28 +0000 (Fri, 22 Nov 2013) | 10 lines [SystemZ] Fix TMHH and TMHL usage for z10 with -O0 I've no idea why I decided to handle TMxx differently from all the other high/low logic operations, but it was a stupid thing to do. The high registers aren't available as separate 32-bit registers on z10, so subreg_h32 can't be used on a GR64 there. I've normally been testing with z196 and with -O3 and so hadn't noticed this until now. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195474 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195398:Bill Wendling2013-11-221-0/+15
| | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r195398 | tstellar | 2013-11-21 16:41:05 -0800 (Thu, 21 Nov 2013) | 7 lines SelectionDAG: Optimize expansion of vec_type = BITCAST scalar_type The legalizer can now do this type of expansion for more type combinations without loading and storing to and from the stack. NOTE: This is a candidate for the 3.4 branch. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195414 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195339:Bill Wendling2013-11-211-32/+0
| | | | | | | | | | | | | | | ------------------------------------------------------------------------ r195339 | chapuni | 2013-11-21 02:55:15 -0800 (Thu, 21 Nov 2013) | 5 lines Revert r195317 (and r195333), "Teach ISel not to optimize 'optnone' functions." It broke, at least, i686 target. It is reproducible with "llc -mtriple=i686-unknown". FYI, it didn't appear to add either "-O0" or "-fast-isel". ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195375 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195333:Bill Wendling2013-11-211-0/+1
| | | | | | | | | | | ------------------------------------------------------------------------ r195333 | kcc | 2013-11-21 01:28:16 -0800 (Thu, 21 Nov 2013) | 1 line add 'REQUIRES: asserts' to a test that uses 'llc -debug'; this fixes the no-asserts build ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195374 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195355:Daniel Sanders2013-11-212-0/+234
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r195355 | dsanders | 2013-11-21 13:24:49 +0000 (Thu, 21 Nov 2013) | 20 lines Add support for legalizing SETNE/SETEQ by inverting the condition code and the result of the comparison. Summary: LegalizeSetCCCondCode can now legalize SETEQ and SETNE by returning the inverse condition and requesting that the caller invert the result of the condition. The caller of LegalizeSetCCCondCode must handle the inverted CC, and they do so as follows: SETCC, BR_CC: Invert the result of the SETCC with SelectionDAG::getNOT() SELECT_CC: Swap the true/false operands. This is necessary for MSA which lacks an integer SETNE instruction. Reviewers: resistor CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D2229 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195363 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195317:Bill Wendling2013-11-211-0/+31
| | | | | | | | | | | | | | ------------------------------------------------------------------------ r195317 | probinson | 2013-11-20 22:33:32 -0800 (Wed, 20 Nov 2013) | 4 lines Teach ISel not to optimize 'optnone' functions. Based on work by Andrea Di Biagio. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195321 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195272:Bill Wendling2013-11-211-0/+16
| | | | | | | | | | | | | | ------------------------------------------------------------------------ r195272 | hfinkel | 2013-11-20 12:54:55 -0800 (Wed, 20 Nov 2013) | 4 lines PPC popcnt[dw] do not have record forms The instruction definitions incorrectly specified that popcntd and popcntw have record forms; they do not. This mistake was causing invalid code generation. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195320 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195318:Bill Wendling2013-11-212-6/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r195318 | void | 2013-11-20 23:04:30 -0800 (Wed, 20 Nov 2013) | 29 lines The basic problem is that some mainstream programs cannot deal with the way clang optimizes tail calls, as in this example: int foo(void); int bar(void) { return foo(); } where the call is transformed to: calll .L0$pb .L0$pb: popl %eax .Ltmp0: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp0-.L0$pb), %eax movl foo@GOT(%eax), %eax popl %ebp jmpl *%eax # TAILCALL However, the GOT references must all be resolved at dlopen() time, and so this approach cannot be used with lazy dynamic linking (e.g. using RTLD_LAZY), which usually populates the PLT with stubs that perform the actual resolving. This patch changes X86TargetLowering::LowerCall() to skip tail call optimization, if the called function is a global or external symbol. Patch by Dimitry Andric! PR15086 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195319 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195129:Bill Wendling2013-11-201-0/+1
| | | | | | | | | | | | ------------------------------------------------------------------------ r195129 | mcinally | 2013-11-19 06:36:00 -0800 (Tue, 19 Nov 2013) | 2 lines Fix assembly operands for the SSE2 cvtsd2ss instruction. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195218 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195094:Bill Wendling2013-11-191-1/+41
| | | | | | | | | | | | | ------------------------------------------------------------------------ r195094 | atrick | 2013-11-18 19:29:59 -0800 (Mon, 18 Nov 2013) | 3 lines Use symbolic operands in the patchpoint folding routine and fix a spilling bug. Fixes <rdar://15487687> [JS] AnyRegCC argument ends up being spilled ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195113 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement AArch64 neon instructions class SIMD lsone and SIMD lone-post.Hao Liu2013-11-192-0/+2432
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195078 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement AArch64 SISD intrinsics for vget_high and vget_low.Jiangning Liu2013-11-191-0/+225
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195074 91177308-0d34-0410-b5e6-96231b3b80d8
* Add predicate for AArch64 crypto instructions.Jiangning Liu2013-11-191-1/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195071 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Fix moveToVALU when the first operand is VSrc.Matt Arsenault2013-11-181-11/+10
| | | | | | | Moving into a VSrc doesn't always work, since it could be replaced with an SGPR later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195042 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Fix multiple SGPR reads when using VCC.Matt Arsenault2013-11-181-3/+18
| | | | | | | No other SGPR operands are allowed, so if VCC is used, move the other to a VGPR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195041 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Implement add i64, but do not yet enable.Matt Arsenault2013-11-181-0/+45
| | | | | | | | Test doesn't actually check the output. I need to fix add i64 being matched for the addressing calculations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195040 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Move patterns to match add / sub to scalar instructionsMatt Arsenault2013-11-184-20/+24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195034 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Enable the IR structurizer by defaultTom Stellard2013-11-183-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195031 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix a crash in the AMDILCFGStrucurizerTom Stellard2013-11-181-0/+62
| | | | | | | The ifPatternMatch() function was not correctly reporting the number of matches in some cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195030 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Fix illegal VGPR->SGPR copy inside of loopTom Stellard2013-11-181-0/+31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195026 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Fix another case of illegal VGPR->SGPR copyTom Stellard2013-11-181-0/+26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195025 91177308-0d34-0410-b5e6-96231b3b80d8
* [PR17978] Mark two ARM/fast-isel tests as XFAIL:vg_leak due to GV.NAKAMURA Takumi2013-11-182-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195010 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix 'ran out of registers' in MIPS32 with FP64 when generating code ↵Daniel Sanders2013-11-181-0/+31
| | | | | | | | | | | | for (ConstantFP 0.0) Fixed an inappropriate use of BuildPairF64 when compiling for MIPS32 with FP64 which resulted in an impossible constraint on the register allocation. It now uses BuildPairF64_64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195007 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement the newly added ACLE functions for ld1/st1 with 2/3/4 vectors.Hao Liu2013-11-182-101/+1269
| | | | | | | The functions are like: vst1_s8_x2 ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194990 91177308-0d34-0410-b5e6-96231b3b80d8
* Testcase for PR17964Bill Wendling2013-11-171-0/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194961 91177308-0d34-0410-b5e6-96231b3b80d8
* DAGCombiner: Partially revert r192795, getNOT was fixed not to create ↵Benjamin Kramer2013-11-171-0/+2
| | | | | | illegal constants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194959 91177308-0d34-0410-b5e6-96231b3b80d8
* Added a size field to the stack map record to handle subregister spills.Andrew Trick2013-11-172-60/+132
| | | | | | | | Implementing this on bigendian platforms could get strange. I added a target hook, getStackSlotRange, per Jakob's recommendation to make this as explicit as possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194942 91177308-0d34-0410-b5e6-96231b3b80d8
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