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* Update to LLVM 3.5a.Stephen Hines2014-04-241-0/+43
* This patch adds support for FPINST/FPINST2 as operands to vmsr/vmrs. These ar...Mihai Popa2013-06-111-0/+8
* ARM: add fstmx and fldmx instructions for assemblyTim Northover2013-05-311-0/+14
* Fix instruction description of VMOV (between two ARM core registers and two s...Richard Barton2012-07-101-0/+21
* Revert r159938 (and r159945) to appease the buildbots.Chad Rosier2012-07-091-21/+0
* Fix instruction description of VMOV (between two ARM core registers and two s...Richard Barton2012-07-091-0/+21
* ARM some VFP tblgen'erated two-operand aliases.Jim Grosbach2012-04-201-2/+7
* Tidy up. Formatting.Jim Grosbach2012-04-201-53/+45
* ARM vmrs system registers mvfr0 and mvfr1 handling.Jim Grosbach2012-03-161-3/+12
* ARM case-insensitive checking for APSR_nzcv.Jim Grosbach2012-03-151-2/+4
* Fix VCVT decoding (between floating-point and fixed-point, Floating-point). ...Kristof Beyls2012-03-151-1/+26
* NEON use vmov.i32 to splat some f32 values into vectors.Jim Grosbach2012-01-201-0/+8
* ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point).Jim Grosbach2011-12-221-0/+12
* ARM VFP optional data type on VMOV GPR<-->SPR.Jim Grosbach2011-12-211-0/+28
* ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns.Jim Grosbach2011-11-151-0/+10
* ARM assembly parsing for two-operand form of 'mul' instruction.Jim Grosbach2011-11-151-0/+6
* ARM VLDR/VSTR instructions don't need a size suffix.Jim Grosbach2011-11-141-27/+27
* ARM optional size suffix for VLDR/VSTR syntax.Jim Grosbach2011-11-111-0/+10
* ARM allow Q registers in vldm/vstm register lists.Jim Grosbach2011-11-111-0/+2
* ARM assembly parsing and encoding for VMOV immediate.Jim Grosbach2011-10-031-5/+9
* ARM parsing/encoding for VCMP/VCMPE.Jim Grosbach2011-10-031-4/+4
* ARM assembly parsing and encoding for VMRS/FMSTAT.Jim Grosbach2011-10-031-2/+4
* Add missing encoding information for some of the GPR<->FP register moves.Owen Anderson2011-08-291-0/+3
* Improve handling of #-0 offsets for many more pre-indexed addressing modes.Owen Anderson2011-08-291-7/+7
* Do AsmMatcher operand classification per-opcode.Jim Grosbach2011-02-101-1/+0
* Add encoding testcases for ARM vcvtr variationsBruno Cardoso Lopes2011-01-261-0/+9
* When matching asm operands, always try to match the most restricted type first.Owen Anderson2011-01-181-0/+1
* Create two new generic classes to represent the following VMRS/VMSR variations:Bruno Cardoso Lopes2011-01-181-0/+8
* Proper encoding for VLDM and VSTM instructions. The register lists for theseBill Wendling2010-11-171-0/+10
* Add encoding for VSTR.Bill Wendling2010-11-041-0/+14
* The MC code couldn't handle ARM LDR instructions with negative offsets:Bill Wendling2010-11-031-1/+20
* Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to workBill Wendling2010-11-021-0/+17
* Use ARM-style comments.Bill Wendling2010-11-011-62/+61
* Mark ARM subtarget features that are available for the assembler.Jim Grosbach2010-11-011-1/+1
* Some instructions end with an "ls" prefix, but it doesn't indicate that they areBill Wendling2010-10-291-0/+160