| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | This patch adds support for FPINST/FPINST2 as operands to vmsr/vmrs. These ar... | Mihai Popa | 2013-06-11 | 1 | -0/+8 |
| * | ARM: add fstmx and fldmx instructions for assembly | Tim Northover | 2013-05-31 | 1 | -0/+14 |
| * | Fix instruction description of VMOV (between two ARM core registers and two s... | Richard Barton | 2012-07-10 | 1 | -0/+21 |
| * | Revert r159938 (and r159945) to appease the buildbots. | Chad Rosier | 2012-07-09 | 1 | -21/+0 |
| * | Fix instruction description of VMOV (between two ARM core registers and two s... | Richard Barton | 2012-07-09 | 1 | -0/+21 |
| * | ARM some VFP tblgen'erated two-operand aliases. | Jim Grosbach | 2012-04-20 | 1 | -2/+7 |
| * | Tidy up. Formatting. | Jim Grosbach | 2012-04-20 | 1 | -53/+45 |
| * | ARM vmrs system registers mvfr0 and mvfr1 handling. | Jim Grosbach | 2012-03-16 | 1 | -3/+12 |
| * | ARM case-insensitive checking for APSR_nzcv. | Jim Grosbach | 2012-03-15 | 1 | -2/+4 |
| * | Fix VCVT decoding (between floating-point and fixed-point, Floating-point). ... | Kristof Beyls | 2012-03-15 | 1 | -1/+26 |
| * | NEON use vmov.i32 to splat some f32 values into vectors. | Jim Grosbach | 2012-01-20 | 1 | -0/+8 |
| * | ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point). | Jim Grosbach | 2011-12-22 | 1 | -0/+12 |
| * | ARM VFP optional data type on VMOV GPR<-->SPR. | Jim Grosbach | 2011-12-21 | 1 | -0/+28 |
| * | ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns. | Jim Grosbach | 2011-11-15 | 1 | -0/+10 |
| * | ARM assembly parsing for two-operand form of 'mul' instruction. | Jim Grosbach | 2011-11-15 | 1 | -0/+6 |
| * | ARM VLDR/VSTR instructions don't need a size suffix. | Jim Grosbach | 2011-11-14 | 1 | -27/+27 |
| * | ARM optional size suffix for VLDR/VSTR syntax. | Jim Grosbach | 2011-11-11 | 1 | -0/+10 |
| * | ARM allow Q registers in vldm/vstm register lists. | Jim Grosbach | 2011-11-11 | 1 | -0/+2 |
| * | ARM assembly parsing and encoding for VMOV immediate. | Jim Grosbach | 2011-10-03 | 1 | -5/+9 |
| * | ARM parsing/encoding for VCMP/VCMPE. | Jim Grosbach | 2011-10-03 | 1 | -4/+4 |
| * | ARM assembly parsing and encoding for VMRS/FMSTAT. | Jim Grosbach | 2011-10-03 | 1 | -2/+4 |
| * | Add missing encoding information for some of the GPR<->FP register moves. | Owen Anderson | 2011-08-29 | 1 | -0/+3 |
| * | Improve handling of #-0 offsets for many more pre-indexed addressing modes. | Owen Anderson | 2011-08-29 | 1 | -7/+7 |
| * | Do AsmMatcher operand classification per-opcode. | Jim Grosbach | 2011-02-10 | 1 | -1/+0 |
| * | Add encoding testcases for ARM vcvtr variations | Bruno Cardoso Lopes | 2011-01-26 | 1 | -0/+9 |
| * | When matching asm operands, always try to match the most restricted type first. | Owen Anderson | 2011-01-18 | 1 | -0/+1 |
| * | Create two new generic classes to represent the following VMRS/VMSR variations: | Bruno Cardoso Lopes | 2011-01-18 | 1 | -0/+8 |
| * | Proper encoding for VLDM and VSTM instructions. The register lists for these | Bill Wendling | 2010-11-17 | 1 | -0/+10 |
| * | Add encoding for VSTR. | Bill Wendling | 2010-11-04 | 1 | -0/+14 |
| * | The MC code couldn't handle ARM LDR instructions with negative offsets: | Bill Wendling | 2010-11-03 | 1 | -1/+20 |
| * | Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work | Bill Wendling | 2010-11-02 | 1 | -0/+17 |
| * | Use ARM-style comments. | Bill Wendling | 2010-11-01 | 1 | -62/+61 |
| * | Mark ARM subtarget features that are available for the assembler. | Jim Grosbach | 2010-11-01 | 1 | -1/+1 |
| * | Some instructions end with an "ls" prefix, but it doesn't indicate that they are | Bill Wendling | 2010-10-29 | 1 | -0/+160 |
