aboutsummaryrefslogtreecommitdiffstats
path: root/test/MC/ARM
Commit message (Expand)AuthorAgeFilesLines
* Support fpv4 for ARM Cortex-M4.Jiangning Liu2012-08-021-0/+4
* Fix #13035, a bug around Thumb instruction LDRD/STRD with negative #0 offset ...Jiangning Liu2012-08-021-0/+12
* Fix #13138, a bug around ARM instruction DSB encoding and decoding issue.Jiangning Liu2012-08-022-0/+142
* Fix #13241, a bug around shift immediate operand for ARM instruction ADR.Jiangning Liu2012-08-022-0/+10
* Fix instruction description of VMOV (between two ARM core registers and two s...Richard Barton2012-07-101-0/+21
* Revert r159938 (and r159945) to appease the buildbots.Chad Rosier2012-07-091-21/+0
* Fix instruction description of VMOV (between two ARM core registers and two s...Richard Barton2012-07-091-0/+21
* Prevent ARM assembler from losing a right shift by #32 applied to a registerRichard Barton2012-07-091-0/+33
* Teach the assembler to use the narrow thumb encodings of various three-regist...Richard Barton2012-07-091-0/+807
* Teach assembler to handle capitalised operation values for DSB instructionsRichard Barton2012-06-271-0/+6
* ARM: Add a better diagnostic for some out of range immediates.Jim Grosbach2012-06-222-8/+8
* Have ARM ELF use correct reloc for "b" instr.Jan Wen Voung2012-06-191-1/+11
* ARM: Define generic HINT instruction.Jim Grosbach2012-06-182-8/+34
* Fix the encoding of the armv7m (MClass) for MSR registers other than aspr,Kevin Enderby2012-06-151-10/+10
* Replace assertion failure for badly formatted CPS instrution with error message.Richard Barton2012-06-141-0/+6
* Refactor data-in-code annotations.Jim Grosbach2012-05-181-1/+1
* Fix the encoding of the armv7m (MClass) for MSR APSR writes which was missingKevin Enderby2012-05-171-4/+28
* Fixed the LLVM ARM v7 assembler and instruction printer for 8-bit immediate o...Silviu Baranga2012-05-111-0/+3
* Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bitsKevin Enderby2012-05-031-2/+2
* ARM: Add missing two-operand VBIC aliases.Jim Grosbach2012-05-021-0/+5
* Disallow YIELD and other allocated nop hints in pre-ARMv6 architectures.Richard Barton2012-05-023-17/+18
* ARM: Add a few missing add->sub aliases w/ 'w' suffix.Jim Grosbach2012-05-011-0/+12
* ARM: allow vanilla expressions for movw/movt.Jim Grosbach2012-05-011-0/+5
* ARM: Thumb add(sp plus register) asm constraints.Jim Grosbach2012-04-272-0/+7
* Fix ARM assembly parsing for upper case condition codes on IT instructions.Richard Barton2012-04-271-0/+13
* Specify cpu to unbreak tests.Evan Cheng2012-04-265-6/+6
* ARM: improved assembler diagnostics for missing CPU features.Jim Grosbach2012-04-241-9/+9
* ARM: Add testcases for two-operand variants of VSRA/VRSRA/VSRI.Jim Grosbach2012-04-232-0/+209
* Add ARM mode tests for the NEON vector shift-accumulate tests.Jim Grosbach2012-04-231-0/+105
* Tidy up. Reformat for ease of reading.Jim Grosbach2012-04-231-95/+102
* ARM: Update NEON assembly two-operand aliases.Jim Grosbach2012-04-202-0/+21
* ARM some VFP tblgen'erated two-operand aliases.Jim Grosbach2012-04-201-2/+7
* Tidy up. Formatting.Jim Grosbach2012-04-201-53/+45
* ARM two-operand forms for vhadd and vhsub instructions.Jim Grosbach2012-04-162-0/+53
* ARM assembly two-operand forms for VRSHL.Jim Grosbach2012-04-161-0/+35
* Tidy up. Test formatting.Jim Grosbach2012-04-161-53/+64
* ARM two-operand aliases for VRHADD instructions.Jim Grosbach2012-04-161-0/+27
* Tidy up. Testcase formatting.Jim Grosbach2012-04-161-13/+14
* ARM 'vuzp.32 Dd, Dm' is a pseudo-instruction.Jim Grosbach2012-04-111-0/+2
* ARM 'vzip.32 Dd, Dm' is a pseudo-instruction.Jim Grosbach2012-04-111-0/+2
* Clean up ARM fused multiply + add/sub support some more: rename some iselEvan Cheng2012-04-111-1/+1
* ARM add missing Thumb1 two-operand aliases for shift-by-immediate.Jim Grosbach2012-04-111-0/+18
* Fix a number of problems with ARM fused multiply add/subtract instructions.Evan Cheng2012-04-111-0/+50
* ARM fix cc_out operand handling for t2SUBrr instructions.Jim Grosbach2012-04-101-0/+12
* ARM assembly aliases for add negative immediates using sub.Jim Grosbach2012-04-051-0/+4
* ARM assembly aliases for two-operand V[R]SHR instructions.Jim Grosbach2012-04-051-0/+70
* ARM assembly parsing for 'msr' plain 'cpsr' operand.Jim Grosbach2012-04-051-0/+2
* ARM assembler should prefer non-aliases encoding of cmp.Jim Grosbach2012-03-301-2/+5
* ARM encoding for VSWP got the second operand incorrect.Jim Grosbach2012-03-301-0/+7
* ARM integrated assembler should encoding choice for add/sub imm.Jim Grosbach2012-03-301-0/+8
generated by cgit v1.1 at 2025-01-24 18:14:11 +0000