| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Added support for disassembling unpredictable swp/swpb ARM instructions. | Silviu Baranga | 2012-04-18 | 1 | -0/+26 |
| * | Fix the bahavior of the disassembler when decoding unpredictable mrs instruct... | Silviu Baranga | 2012-04-18 | 1 | -0/+18 |
| * | Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the ... | Silviu Baranga | 2012-04-18 | 2 | -0/+17 |
| * | Fixed decoding for the ARM cdp2 instruction. The restriction on the coprocess... | Silviu Baranga | 2012-04-18 | 1 | -0/+3 |
| * | Add suport for unpredicatble cases of the cmp, tst, teq and cmnz ARM instruct... | Silviu Baranga | 2012-04-18 | 1 | -0/+30 |
| * | Fix ARM disassembly of VLD2 (single 2-element structure to all lanes) | Kevin Enderby | 2012-04-17 | 2 | -0/+75 |
| * | Fixed a case of ARM disassembly getting an assert on a bad encoding | Kevin Enderby | 2012-04-11 | 1 | -0/+13 |
| * | Fix ARM disassembly of VLD instructions with writebacks. And add test a case | Kevin Enderby | 2012-04-11 | 2 | -0/+364 |
| * | Fix a number of problems with ARM fused multiply add/subtract instructions. | Evan Cheng | 2012-04-11 | 1 | -0/+37 |
| * | Added support for unpredictable ADC/SBC instructions on ARM, and also fixed s... | Silviu Baranga | 2012-04-05 | 1 | -0/+17 |
| * | Added support for handling unpredictable arithmetic instructions on ARM. | Silviu Baranga | 2012-04-05 | 2 | -12/+7 |
| * | Added fix in TableGen instruction decoder generation. The decoder now breaks ... | Silviu Baranga | 2012-04-02 | 1 | -0/+15 |
| * | Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnu | Eli Bendersky | 2012-03-25 | 1 | -8/+1 |
| * | Added soft fail checks for the disassembler when decoding some corner cases o... | Silviu Baranga | 2012-03-22 | 3 | -2/+21 |
| * | Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or LDR... | Silviu Baranga | 2012-03-22 | 1 | -0/+22 |
| * | Added soft fail cases for the disassembler when decoding MUL instructions on ... | Silviu Baranga | 2012-03-22 | 1 | -0/+17 |
| * | Fix ARM disassembly of VST1 and VST2 instructions with writeback. And add test | Kevin Enderby | 2012-03-21 | 2 | -0/+368 |
| * | The ARM instructions that have an unpredictable behavior when the pc register... | Silviu Baranga | 2012-03-20 | 5 | -5/+17 |
| * | Fix a bug in the ARM disassembly of the neon VLD2 all lanes instruction. | Kevin Enderby | 2012-03-06 | 2 | -0/+14 |
| * | Change ARMInstPrinter::printPredicateOperand() so it will not abort if it | Kevin Enderby | 2012-03-01 | 1 | -0/+18 |
| * | Replace all instances of dg.exp file with lit.local.cfg, since all tests are ... | Eli Bendersky | 2012-02-16 | 2 | -6/+13 |
| * | Teach the MC and disassembler about SoftFail, and hook it up to UNPREDICTABLE... | James Molloy | 2012-02-09 | 1 | -0/+5 |
| * | ARM NEON VST2 assembly parsing and encoding. | Jim Grosbach | 2011-12-14 | 1 | -1/+1 |
| * | Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VM... | Owen Anderson | 2011-11-15 | 1 | -0/+6 |
| * | ARM VLDR/VSTR instructions don't need a size suffix. | Jim Grosbach | 2011-11-14 | 2 | -17/+17 |
| * | Simplify some uses of utohexstr. | Benjamin Kramer | 2011-11-07 | 3 | -23/+23 |
| * | Fix the issue that r143552 was trying to address the _right_ way. One-regist... | Owen Anderson | 2011-11-02 | 1 | -0/+4 |
| * | Fix disassembly of some VST1 instructions. | Owen Anderson | 2011-11-01 | 1 | -1/+2 |
| * | More not-crashing NEON disassembly updates for the vld refactoring. | Owen Anderson | 2011-10-31 | 1 | -0/+2 |
| * | Fix illegal disassembly testcase. | Owen Anderson | 2011-10-28 | 1 | -2/+2 |
| * | Reapply r143202, with a manual decoding hook for SWP. This change inadvertan... | Owen Anderson | 2011-10-28 | 1 | -1/+1 |
| * | Add testcase for r143162. | Owen Anderson | 2011-10-27 | 1 | -0/+4 |
| * | Fix a NEON disassembly case that was broken in the recent refactorings. As m... | Owen Anderson | 2011-10-24 | 1 | -0/+4 |
| * | Revert r142618, r142622, and r142624, which were based on an incorrect readin... | Owen Anderson | 2011-10-20 | 2 | -5/+55 |
| * | Fix decoding tests for fixed MSR encodings. | Owen Anderson | 2011-10-20 | 2 | -55/+5 |
| * | Thumb2 assembly parsing and encoding for LDC/STC. | Jim Grosbach | 2011-10-12 | 1 | -1/+1 |
| * | Update test for r141704. | Jim Grosbach | 2011-10-11 | 1 | -3/+3 |
| * | Check in a patch that has already been code reviewed by Owen that I'd forgott... | James Molloy | 2011-09-28 | 2 | -0/+13 |
| * | Fix an incorrect decoder test. | Owen Anderson | 2011-09-26 | 1 | -2/+2 |
| * | Fix incorrect disassembly test. | Owen Anderson | 2011-09-23 | 1 | -1/+1 |
| * | Post-index loads/stores in still need to print the post-indexed immediate, ev... | Owen Anderson | 2011-09-23 | 1 | -0/+7 |
| * | Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid t... | Owen Anderson | 2011-09-23 | 1 | -2/+2 |
| * | Print out immediate offset versions of PC-relative load/store instructions as... | Owen Anderson | 2011-09-21 | 2 | -1/+3 |
| * | Port over more Thumb2 encoding tests to decoding tests. | Owen Anderson | 2011-09-20 | 1 | -0/+608 |
| * | Handle STRT (and friends) like LDRT (and friends) for decoding purposes. Por... | Owen Anderson | 2011-09-19 | 1 | -0/+150 |
| * | Add a testcase for another corner-case decoding. | Owen Anderson | 2011-09-16 | 1 | -0/+2 |
| * | Fix disassembly of Thumb2 BFI instructions with bit range of [0, 32). | Owen Anderson | 2011-09-16 | 1 | -0/+2 |
| * | Add fixed bits to correctly distinguish Thumb2 SSAT/SSAT16's. | Owen Anderson | 2011-09-16 | 1 | -0/+7 |
| * | Fix disassembly of Thumb2 LDRSH with a #-0 offset. | Owen Anderson | 2011-09-16 | 1 | -1/+2 |
| * | Port over more Thumb2 assembly tests to disassembly tests. | Owen Anderson | 2011-09-16 | 1 | -0/+95 |
