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* The ARM NEON vector compare instructions take three arguments. However, the Joel Jones2013-02-141-1/+67
* death to extra whitespaceKay Tiong Khoo2013-02-141-20/+20
* added basic support for Intel ADX instructionsKay Tiong Khoo2013-02-142-0/+36
* Revert r15266. This fixes llvm.org/pr15266.Rafael Espindola2013-02-142-20/+6
* Make ARMAsmParser accept the correct alignment specifier syntax in instructions.Kristof Beyls2013-02-145-152/+168
* [ms-inline asm] Add support for lexing binary integers with a [bB] suffix.Chad Rosier2013-02-122-6/+20
* added test cases for r174920 (prefetch disassembly)Kay Tiong Khoo2013-02-121-0/+6
* [ms-inline asm] Add support for lexing hexidecimal integers with a [hH] suffix.Chad Rosier2013-02-121-0/+26
* *fixed disassembly of some i386 system insts with intel syntaxKay Tiong Khoo2013-02-111-0/+13
* AArch64: Undo change to how test was runTim Northover2013-02-111-1/+2
* Make use of DiagnosticType to provide better AArch64 diagnostics.Tim Northover2013-02-111-501/+504
* [mips] Add definition of JALR instruction which has two register operands. Ch...Akira Hatanaka2013-02-071-0/+8
* Add AArch64 CRC32 instructionsTim Northover2013-02-062-0/+34
* Add icache prefetch operations to AArch64Tim Northover2013-02-062-0/+50
* [MC] Bundle alignment: Invalidate relaxed fragmentsDerek Schuff2013-02-051-0/+16
* This patch that sets the Mips ELF header flag for Jack Carter2013-02-051-0/+8
* This patch that sets the EmitAlias flag in td files Jack Carter2013-02-052-10/+10
* Add explicit triples to AArch64 testsTim Northover2013-02-011-2/+2
* [MC] bundle alignment: prevent padding instructions from crossing bundle boun...Derek Schuff2013-01-312-2/+108
* Add AArch64 as an experimental target.Tim Northover2013-01-3123-0/+13915
* Add a special ARM trap encoding for NaCl.Eli Bendersky2013-01-301-4/+11
* This patch implements runtime ARM specificJack Carter2013-01-302-1/+13
* This patch implements runtime Mips specificJack Carter2013-01-301-0/+55
* This patch reworks how llvm targets set Jack Carter2013-01-301-0/+1
* [MC][COFF] Delay handling symbol aliases when writingMichael J. Spencer2013-01-291-0/+11
* Merge SSE and AVX shuffle instructions in the comment printer.Craig Topper2013-01-291-0/+225
* Fix 256-bit PALIGNR comment decoding to understand that it works on independe...Craig Topper2013-01-281-0/+15
* [XCore] Add missing l2rus instructions.Richard Osborne2013-01-271-0/+6
* [XCore] Add missing l2r instructions.Richard Osborne2013-01-271-0/+12
* [XCore] Add missing 1r instructions.Richard Osborne2013-01-271-0/+27
* [XCore] Add missing 0r instructions.Richard Osborne2013-01-271-0/+51
* X86: Decode PALIGN operands so I don't have to do it in my head.Benjamin Kramer2013-01-261-0/+31
* Add instruction encodings / disassembly support for l4r instructions.Richard Osborne2013-01-251-0/+11
* Now that llvm-dwarfdump supports flags to specify which DWARF section to dump,Eli Bendersky2013-01-256-7/+7
* Add instruction encodings / disassembly support for l5r instructions.Richard Osborne2013-01-251-0/+11
* This patch implements parsing the .wordJack Carter2013-01-251-1/+4
* Add instruction encodings / disassembly support for l6r instructions.Richard Osborne2013-01-231-0/+5
* Add instruction encodings / disassembly support for u10 / lu10 instructions.Richard Osborne2013-01-221-0/+14
* Add a warning when there is a macro defintion that has named parameters butKevin Enderby2013-01-221-0/+14
* Have the integrated assembler give an error if $1 is used as an identifier inKevin Enderby2013-01-221-0/+5
* Add forgotten test case for the x32 commitEli Bendersky2013-01-221-0/+24
* X86: Make sure we account for the FMA4 register immediate value, otherwise ri...Benjamin Kramer2013-01-221-0/+61
* [MC/Mach-O] Load commands are supposed to 8-byte aligned on 64-bit.Daniel Dunbar2013-01-221-1/+9
* Add instruction encodings / disassembly support for u6 / lu6 instructions.Richard Osborne2013-01-211-0/+50
* Add instruction encoding / disassembly support for ru6 / lru6 instructions.Richard Osborne2013-01-211-0/+80
* Add instruction encodings / disassembly support for l2rus instructions.Richard Osborne2013-01-201-0/+11
* Add instruction encodings / disassembly support for l3r instructions.Richard Osborne2013-01-201-0/+44
* Add instruction encodings / disassembler support for 2rus instructions.Richard Osborne2013-01-201-0/+23
* Add instruction encodings / disassembly support 3r instructions.Richard Osborne2013-01-201-0/+38
* This is a resubmittal. For some reason it broke the bots yesterdayJack Carter2013-01-181-0/+31
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