| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Tweak ARM assembly parsing and printing of MSR instruction. | Jim Grosbach | 2011-07-19 | 4 | -42/+67 |
| * | ARM assembly parsing of MRS instruction. | Jim Grosbach | 2011-07-19 | 2 | -3/+13 |
| * | ARM assembly parsing for MRC/MRC2/MRRC/MRRC2. | Jim Grosbach | 2011-07-19 | 1 | -0/+14 |
| * | Move mr[r]c[2] ARM tests and tidy up a bit. | Jim Grosbach | 2011-07-19 | 2 | -10/+19 |
| * | ARM testcases for MOVT. | Jim Grosbach | 2011-07-19 | 2 | -0/+15 |
| * | ARM assembly parsing for MOV (register). | Jim Grosbach | 2011-07-19 | 2 | -0/+25 |
| * | ARM assembly parsing for MOV (immediate). | Jim Grosbach | 2011-07-19 | 3 | -5/+35 |
| * | Whitespace. | Jim Grosbach | 2011-07-19 | 1 | -1/+1 |
| * | Make the disassembler able to disassemble a bunch of instructions with names ... | Eli Friedman | 2011-07-16 | 1 | -0/+26 |
| * | PR10370: Make sure we know how to relax push correctly on x86-64. | Eli Friedman | 2011-07-15 | 1 | -5/+5 |
| * | Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues ... | Owen Anderson | 2011-07-15 | 1 | -1/+1 |
| * | ARM diagnostic when 's' suffix on mnemonic that can't set flags. | Jim Grosbach | 2011-07-14 | 1 | -0/+6 |
| * | Add some testcases for ARM MLA/MLS instructions. | Jim Grosbach | 2011-07-14 | 2 | -3/+23 |
| * | ARM MCRR/MCRR2 immediate operand range checking. | Jim Grosbach | 2011-07-14 | 3 | -5/+14 |
| * | ARM MCR/MCR2 assembly parsing operand constraints. | Jim Grosbach | 2011-07-14 | 3 | -4/+28 |
| * | Enable some tests we now handle correctly. | Jim Grosbach | 2011-07-14 | 1 | -18/+9 |
| * | Update ARM Assembly of LDM/STM. | Jim Grosbach | 2011-07-14 | 2 | -44/+58 |
| * | ARM ISB assembly parsing tests. | Jim Grosbach | 2011-07-14 | 2 | -2/+10 |
| * | ARM ISB instruction assembly parsing. | Jim Grosbach | 2011-07-14 | 1 | -1/+1 |
| * | ARM tests for EOR instruction parsing and encoding. | Jim Grosbach | 2011-07-14 | 1 | -0/+57 |
| * | Remove duplicate tests. | Jim Grosbach | 2011-07-14 | 1 | -24/+0 |
| * | ARM Assembler support for DSB instruction. | Jim Grosbach | 2011-07-14 | 1 | -0/+31 |
| * | ARM Assembler support for DMB instruction. | Jim Grosbach | 2011-07-13 | 2 | -24/+32 |
| * | ARM Assembler support for DBG instruction. | Jim Grosbach | 2011-07-13 | 2 | -0/+19 |
| * | ARM parsing and encoding tests for CMN/CMP. | Jim Grosbach | 2011-07-13 | 1 | -0/+59 |
| * | Shuffle ARM assembly tests a bit. | Jim Grosbach | 2011-07-13 | 2 | -10/+22 |
| * | Range checking for CDP[2] immediates. | Jim Grosbach | 2011-07-13 | 2 | -0/+27 |
| * | Fix predicates for Thumb co-processor instructions. | Jim Grosbach | 2011-07-13 | 2 | -15/+15 |
| * | Testcases for ARM assembly BX/BXJ instructions. | Jim Grosbach | 2011-07-13 | 1 | -2/+24 |
| * | Testcases for ARM assembly BLX/BL instructions. | Jim Grosbach | 2011-07-13 | 1 | -0/+17 |
| * | Range checking for 16-bit immediates in ARM assembly. | Jim Grosbach | 2011-07-13 | 2 | -4/+8 |
| * | Add tests for ARM parsing of 'BKPT' instruction. | Jim Grosbach | 2011-07-13 | 1 | -0/+9 |
| * | Fix copy-pasto. | Jim Grosbach | 2011-07-13 | 1 | -1/+1 |
| * | Add tests for ARM parsing of 'BIC' instruction. | Jim Grosbach | 2011-07-13 | 1 | -0/+58 |
| * | Add some FIXMEs. | Jim Grosbach | 2011-07-13 | 1 | -0/+16 |
| * | Add tests for ARM parsing of 'AND' instruction. | Jim Grosbach | 2011-07-13 | 1 | -0/+58 |
| * | Improve ARM assembly parsing diagnostics a bit. | Jim Grosbach | 2011-07-13 | 1 | -0/+43 |
| * | Add tests for ARM parsing of 'ADD' instruction | Jim Grosbach | 2011-07-13 | 1 | -0/+63 |
| * | Destination register operand is optional for ADC and SBC ARM. | Jim Grosbach | 2011-07-13 | 1 | -0/+36 |
| * | Flesh out ARM Parser support for shifted-register operands. | Jim Grosbach | 2011-07-13 | 1 | -0/+48 |
| * | Add check for predicate w/o S bit. | Jim Grosbach | 2011-07-12 | 1 | -0/+2 |
| * | Fix recognition of ARM 'adcs' mnemonic. | Jim Grosbach | 2011-07-11 | 1 | -0/+31 |
| * | Simplify printing of ARM shifted immediates. | Jim Grosbach | 2011-07-11 | 2 | -8/+7 |
| * | - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo | Evan Cheng | 2011-07-11 | 1 | -1/+2 |
| * | Add support for ARM / Thumb mode switching with .code 16 and .code 32. | Evan Cheng | 2011-07-08 | 1 | -0/+16 |
| * | Change some ARM subtarget features to be single bit yes/no in order to sink t... | Evan Cheng | 2011-07-07 | 1 | -2/+2 |
| * | Update MC/ELF/relocation.s with change to X86 PUSH64i8 in r134501. | Kevin Enderby | 2011-07-06 | 1 | -5/+5 |
| * | Changed the X86 PUSH64i8 record to use the i64i8imm ParserMatchClass so that a | Kevin Enderby | 2011-07-06 | 1 | -0/+6 |
| * | Add assembler/disassembler support for non-AVX pclmulqdq. While I'm here, use... | Eli Friedman | 2011-07-05 | 1 | -0/+16 |
| * | Recognize the xstorerng alias for VIA PadLock's xstore instruction. | Joerg Sonnenberger | 2011-06-30 | 1 | -0/+4 |
