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* DISubrange supports unsigned lower/upper array bounds, so let's not fake it i...Devang Patel2011-11-171-0/+37
* Fix an overly general check in SimplifyIndvar to handle useless phi cycles.Andrew Trick2011-11-171-0/+29
* fall back to explicit list of allowed linkages when instrumenting globals in ...Kostya Serebryany2011-11-171-0/+6
* When fast iseling a GEP, accumulate the offset rather than emitting a series ofChad Rosier2011-11-171-0/+65
* Add support for custom names for library functions in TargetLibraryInfo. Add...Eli Friedman2011-11-171-0/+30
* build/make/test: Get rid of unused BUGPOINT_TOPTS variable.Daniel Dunbar2011-11-161-5/+0
* Make sure to replace the chain properly when DAGCombining a LOAD+EXTRACT_VECT...Eli Friedman2011-11-161-1/+1
* Remove obsolete test.Jim Grosbach2011-11-161-58/+0
* Generalize the fixup info for ARM mode.Jim Grosbach2011-11-161-2/+2
* Update test for r144842.Jim Grosbach2011-11-161-1/+1
* Another missing X86ISD::MOVLPD pattern. rdar://10450317Evan Cheng2011-11-161-0/+17
* Disable expensive two-address optimizations at -O0. rdar://10453055Evan Cheng2011-11-162-5/+4
* Fix typo in test.Nick Lewycky2011-11-161-1/+1
* Merge isObjectPointerWithTrustworthySize with getPointerSize. Use it whenNick Lewycky2011-11-161-0/+38
* Fix testcase.Eli Friedman2011-11-161-1/+0
* CONCAT_VECTORS can have more than two operands. PR11389.Eli Friedman2011-11-161-0/+9
* AddressSanitizer, first commit (compiler module only)Kostya Serebryany2011-11-162-0/+17
* Fix SCEV overly optimistic back edge taken count for multi-exit loops.Andrew Trick2011-11-163-2/+53
* ARM assembly parsing for register range syntax for VLD/VST register lists.Jim Grosbach2011-11-151-0/+8
* AVX: Add support for vbroadcast from BUILD_VECTOR and refactor some of the vb...Nadav Rotem2011-11-151-3/+0
* test/CodeGen/X86/dec-eflags-lower.ll: Relax expression for win32 x64.NAKAMURA Takumi2011-11-151-1/+1
* ARM assembly parsing two operand forms for shift instructions.Jim Grosbach2011-11-151-0/+8
* Added custom lowering for load->dec->store sequence in x86 when the EFLAGS re...Pete Cooper2011-11-151-0/+29
* ARM alternate size suffices for VTRN instructions.Jim Grosbach2011-11-151-0/+60
* ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns.Jim Grosbach2011-11-151-0/+10
* ARM assembly parsing for two-operand form of 'mul' instruction.Jim Grosbach2011-11-151-0/+6
* ARM assembly parsing for two-operand form of 'mul' instruction.Jim Grosbach2011-11-151-0/+2
* Testcase for r144684.Jim Grosbach2011-11-151-0/+2
* Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VM...Owen Anderson2011-11-151-0/+6
* Thumb2 assembly parsing for mul.w in IT block fix.Jim Grosbach2011-11-151-0/+4
* We currently use a callback to handle an IL pass deleting a BB that stillRafael Espindola2011-11-151-0/+19
* Revert r144611 and r144613.Jakob Stoklund Olesen2011-11-152-3/+3
* Rather than trying to use the loop block sequence *or* the functionChandler Carruth2011-11-151-1/+72
* Properly qualify AVX2 specific parts of execution dependency table. Also enab...Craig Topper2011-11-152-14/+41
* Really fix test.Jakob Stoklund Olesen2011-11-151-1/+1
* Allow for depencendy-breaking instructions before cvt*.Jakob Stoklund Olesen2011-11-152-2/+2
* Add vmov.f32 to materialize f32 immediate splats which cannot be handled byEvan Cheng2011-11-152-3/+20
* Break false dependencies before partial register updates.Jakob Stoklund Olesen2011-11-151-0/+41
* ARM parsing datatype suffix variants for non-writeback VST1 instructions.Jim Grosbach2011-11-141-0/+21
* ARM parsing datatype suffix variants for non-writeback VLD1 instructions.Jim Grosbach2011-11-141-0/+28
* ARM parsing optional datatype suffix for VAND/VEOR/VORR instructions.Jim Grosbach2011-11-141-0/+177
* ARM VLDR/VSTR instructions don't need a size suffix.Jim Grosbach2011-11-1422-94/+94
* Refactor capture tracking (which already had a couple flags for whether returnsNick Lewycky2011-11-141-0/+25
* Add newline to end of file. Thanks, Eli.Chad Rosier2011-11-141-1/+1
* Add support for inlining small memcpys.Chad Rosier2011-11-141-3/+31
* Fix a performance regression from r144565. Positive offsets were being loweredChad Rosier2011-11-141-0/+55
* Add a missing pattern for X86ISD::MOVLPD. rdar://10436044Evan Cheng2011-11-141-0/+18
* Add support for Thumb load/stores with negative offsets.Chad Rosier2011-11-141-0/+168
* Teach two-address pass to re-schedule two-address instructions (or the killEvan Cheng2011-11-143-18/+15
* Changed SSE4/AVX <2 x i64> extract and insert ops to be Custom loweredPete Cooper2011-11-141-0/+26
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