aboutsummaryrefslogtreecommitdiffstats
path: root/test
Commit message (Collapse)AuthorAgeFilesLines
...
* Add support for several vector shifts operations while in AVX mode. Fix PR10581Bruno Cardoso Lopes2011-08-081-0/+64
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137067 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix up the patterns for SXTB, SXTH, UXTB, and UXTH so that they are ↵Eli Friedman2011-08-081-0/+29
| | | | | | correctly active without HasT2ExtractPack. PR10611. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137061 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't clobber pending ST regs when FP regs are killed.Jakob Stoklund Olesen2011-08-081-0/+11
| | | | | | | | | | | | | | | | | | | X86FloatingPoint keeps track of pending ST registers for an upcoming inline asm instruction with fixed stack register constraints. It does this by remembering which FP register holds the value that should appear at a fixed stack position for the inline asm. When that FP register is killed before the inline asm, make sure to duplicate it to a scratch register, so the ST register still has a live FP reference. This could happen when the same FP register was copied to two ST registers, or when a spill instruction is inserted between the ST copy and the inline asm. This fixes PR10602. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137050 91177308-0d34-0410-b5e6-96231b3b80d8
* Made SCEV's UDiv expressions more canonical. When dividing aAndrew Trick2011-08-061-0/+56
| | | | | | | | | | | | | | | | | | | | | | | | recurrence, the initial values low bits can sometimes be ignored. To take advantage of this, added FoldIVUser to IndVarSimplify to fold an IV operand into a udiv/lshr if the operator doesn't affect the result. -indvars -disable-iv-rewrite now transforms i = phi i4 i1 = i0 + 1 idx = i1 >> (2 or more) i4 = i + 4 into i = phi i4 idx = i0 >> ... i4 = i + 4 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137013 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM load instruction shifted register index operands.Jim Grosbach2011-08-051-0/+4
| | | | | | | Parsing and encoding for shifted index operands for load instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136986 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM indexed load assembly parsing and encoding.Jim Grosbach2011-08-051-0/+16
| | | | | | | | More parsing support for indexed loads. Fix pre-indexed with writeback parsing for register offsets and handle basic post-indexed offsets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136982 91177308-0d34-0410-b5e6-96231b3b80d8
* Add ARM LDR parsing tests.Jim Grosbach2011-08-051-0/+26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136977 91177308-0d34-0410-b5e6-96231b3b80d8
* We need to map DebugLoc. It leads to Fuction * (through subprogram entry ↵Devang Patel2011-08-042-0/+49
| | | | | | node) which should be appropriately mapped. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136910 91177308-0d34-0410-b5e6-96231b3b80d8
* Linke NamedMDNodes after linking global values as comment suggests.Devang Patel2011-08-042-0/+58
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136909 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the bitwidth of the remaining fields.Rafael Espindola2011-08-0450-540/+536
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136884 91177308-0d34-0410-b5e6-96231b3b80d8
* print st_shndx with the correct number of bits.Rafael Espindola2011-08-0425-82/+82
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136880 91177308-0d34-0410-b5e6-96231b3b80d8
* print st_other with the correct number of bits.Rafael Espindola2011-08-0425-84/+84
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136877 91177308-0d34-0410-b5e6-96231b3b80d8
* print st_type with the correct number of bits.Rafael Espindola2011-08-0428-95/+95
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136875 91177308-0d34-0410-b5e6-96231b3b80d8
* Print st_bind with the correct number of bits.Rafael Espindola2011-08-0431-99/+101
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136874 91177308-0d34-0410-b5e6-96231b3b80d8
* Print r_sym with the correct number of bits.Rafael Espindola2011-08-048-29/+29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136873 91177308-0d34-0410-b5e6-96231b3b80d8
* Print r_type with the correct number of bits.Rafael Espindola2011-08-0410-42/+44
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136872 91177308-0d34-0410-b5e6-96231b3b80d8
* Another counter goes decimal.Rafael Espindola2011-08-0430-95/+95
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136871 91177308-0d34-0410-b5e6-96231b3b80d8
* Change anther counter to decimal.Rafael Espindola2011-08-0437-167/+167
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136870 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't print a counter in hex.Rafael Espindola2011-08-0424-38/+38
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136869 91177308-0d34-0410-b5e6-96231b3b80d8
* Print all the bits in the addend.Rafael Espindola2011-08-0426-129/+123
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136867 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix http://llvm.org/bugs/show_bug.cgi?id=10568Jason W Kim2011-08-041-0/+13
| | | | | | Move the reloc size assert into AsmBackend - where it is more apropos. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136855 91177308-0d34-0410-b5e6-96231b3b80d8
* Only access both operands of an INSERT_SUBVECTOR if it is an INSERT_SUBVECTOR.Bill Wendling2011-08-041-0/+23
| | | | | | | Fixes PR10527. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136853 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM refactoring assembly parsing of memory address operands.Jim Grosbach2011-08-033-6/+11
| | | | | | | | | | | | | | | | | | | | | | | | Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136845 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove underscore that's breaking linux buildbots.Benjamin Kramer2011-08-031-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136833 91177308-0d34-0410-b5e6-96231b3b80d8
* Use MachineBranchProbabilityInfo in If-Conversion instead of its own heuristics.Jakub Staszak2011-08-034-18/+19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136826 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the LowerSetJmp pass. It wasn't used effectively by any of the targets.Bill Wendling2011-08-033-50/+0
| | | | | | | This is some of my original LLVM code. *wipes tear* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136821 91177308-0d34-0410-b5e6-96231b3b80d8
* SCEV: Use AssertingVH to catch dangling BasicBlock* when passes forgetAndrew Trick2011-08-031-0/+88
| | | | | | | to notify SCEV of a change. Add forgetLoop in a couple of those places. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136797 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle IMPLICIT_DEF instructions in X86FloatingPoint.Jakob Stoklund Olesen2011-08-031-1/+20
| | | | | | This fixes PR10575. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136787 91177308-0d34-0410-b5e6-96231b3b80d8
* fix PR10286, a problem with the .ll printer handling block addresses that ↵Chris Lattner2011-08-031-0/+23
| | | | | | are out-of-scope. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136768 91177308-0d34-0410-b5e6-96231b3b80d8
* Use byte offset, instead of element number, to access merged global.Devang Patel2011-08-031-0/+124
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136759 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix logical error when detecting lifetime intrinsics.Nick Lewycky2011-08-031-0/+11
| | | | | | | | | | Don't replace a gep/bitcast with 'undef' because that will form a "free(undef)" which in turn means "unreachable". What we wanted was a no-op. Instead, analyze the whole tree and look for all the instructions we need to delete first, then delete them second, not relying on the use_list to stay consistent. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136752 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach InstCombine that lifetime intrincs aren't a real user on the result of aNick Lewycky2011-08-021-1/+13
| | | | | | | malloc call. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136732 91177308-0d34-0410-b5e6-96231b3b80d8
* Lifetime intrinsics on undef are dead.Nick Lewycky2011-08-021-1/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136722 91177308-0d34-0410-b5e6-96231b3b80d8
* Assume .cfi_startproc is the first thing in a function. If the function isRafael Espindola2011-08-021-0/+21
| | | | | | | | | externally visable, create a local symbol to use in the CFE. If not, use the function label itself. Fixes PR10420. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136716 91177308-0d34-0410-b5e6-96231b3b80d8
* Make this kind of lowering to be supported by 256-bit instructions:Bruno Cardoso Lopes2011-08-021-0/+32
| | | | | | | | | shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0> To: shuffle (vload ptr)), undef, <1, 1, 1, 1> Fix PR10494 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136691 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove empty test.Benjamin Kramer2011-08-021-0/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136675 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r136503 and r136480 in an effort to fix non-determinism in the ↵Owen Anderson2011-08-021-38/+0
| | | | | | llvm-gcc buildbots on i386. Devang is looking into the root cause. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136674 91177308-0d34-0410-b5e6-96231b3b80d8
* Add v4f64 -> v2f32 fp_round support. Also add a testcase to exerciseBruno Cardoso Lopes2011-08-011-0/+7
| | | | | | | the legalizer. This commit together with the two previous ones fixes PR10495. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136654 91177308-0d34-0410-b5e6-96231b3b80d8
* Since vectors with all ones can't be created with a 256-bit instruction,Bruno Cardoso Lopes2011-08-011-0/+9
| | | | | | | | avoid returning early for v8i32 types, which would only be valid for vector with all zeros. Also split the handling of zeros and ones into separate checking logic since they are handled differently. This fixes PR10547 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136642 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix crash with varargs function with no named parameters.Richard Osborne2011-08-011-0/+17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136623 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a small gep optimization I noticed was missing while reading some IL.Rafael Espindola2011-07-311-0/+20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136585 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove InvalidateStructLayoutInfo from the ocaml bindings.Benjamin Kramer2011-07-311-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136582 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r136253, r136263, r136269, r136313, r136325, r136326, r136329, r136338,Bill Wendling2011-07-301-54/+0
| | | | | | | | | r136339, r136341, r136369, r136387, r136392, r136396, r136429, r136430, r136444, r136445, r136446, r136253 pending review. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136556 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Don't check liveness of unallocatable registers."Jakob Stoklund Olesen2011-07-301-1/+1
| | | | | | | The ARM target depends on CPSR liveness being tracked after register allocation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136548 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't check liveness of unallocatable registers.Jakob Stoklund Olesen2011-07-291-1/+1
| | | | | | | | | | | | This includes registers like EFLAGS and ST0-ST7. We don't check for liveness issues in the verifier and scavenger because registers will never be allocated from these classes. While in SSA form, we do care about the liveness of unallocatable unreserved registers. Liveness of EFLAGS and ST0 neds to be correct for MachineDCE and MachineSinking. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136541 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for the 'Q' constraint.Eric Christopher2011-07-291-0/+12
| | | | | | | Fixes rdar://9866494 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136523 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM SRS instruction parsing, diassembly and encoding support.Jim Grosbach2011-07-292-2/+53
| | | | | | | | | Fix the instruction encoding for operands. Refactor mode to use explicit instruction definitions per FIXME to be more consistent with loads/stores. Fix disassembler accordingly. Add tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136509 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up debug info after reassociation.Devang Patel2011-07-291-0/+38
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136480 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing and encoding for RFE instruction.Jim Grosbach2011-07-291-0/+50
| | | | | | | | | | | | Fill in the missing fixed bits and the register operand bits of the instruction encoding. Refactor the definition to make the mode explicit, which is consistent with how loads and stores are normally represented and makes parsing much easier. Add parsing aliases for pseudo-instruction variants. Update the disassembler for the new representations. Add tests for parsing and encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136479 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM update tests for CPS instruction.Jim Grosbach2011-07-292-9/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136472 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.1 at 2024-10-27 09:16:26 +0000