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* Implement fastcc calling convention for MIPS.Akira Hatanaka2012-06-131-0/+253
* Fix pattern for MKMSK instruction.Richard Osborne2012-06-131-0/+11
* Revert "Allow SROA to look at a vector type and see if the offset is out of r...Pete Cooper2012-06-131-4/+7
* Allow SROA to look at a vector type and see if the offset is out of range to ...Pete Cooper2012-06-131-7/+4
* It is possible for several constants which aren't individually absorbing toDuncan Sands2012-06-131-0/+11
* Fix intrinsics for XOP frczss/sd instructions. These instructions only take o...Craig Topper2012-06-131-12/+12
* SimplifyCFG: fold unconditional branch to its predecessor if profitable.Manman Ren2012-06-131-0/+33
* disable use of directive .set nomicromipsAkira Hatanaka2012-06-131-1/+1
* sched: fix latency of memory dependence chain edges for consistency.Andrew Trick2012-06-131-0/+41
* Use std::map rather than SmallMap because SmallMap assumes that the value hasDuncan Sands2012-06-122-13/+16
* [arm-fast-isel] Add support for -arm-long-calls.Chad Rosier2012-06-122-0/+64
* Now that Reassociate's LinearizeExprTree can look through arbitrary expressionDuncan Sands2012-06-121-0/+252
* Fix test that depends on register allocation.Jakob Stoklund Olesen2012-06-111-5/+4
* Fix test case to work on ARM.Jakob Stoklund Olesen2012-06-111-2/+3
* Re-enable the CMN instruction.Bill Wendling2012-06-111-0/+22
* InstCombine: Turn (zext A) == (B & (1<<X)-1) into A == (trunc B), narrowing t...Benjamin Kramer2012-06-101-0/+22
* Enable ILP scheduling for all nodes by default on PPC.Hal Finkel2012-06-103-4/+4
* Add AutoUpgrade support for the SSE4 ptest intrinsics.Nadav Rotem2012-06-102-0/+44
* Improve ext/trunc patterns on PPC64.Hal Finkel2012-06-091-0/+1
* Replace XOP vpcom intrinsics with fewer intrinsics that take the immediate as...Craig Topper2012-06-091-0/+56
* Enable tail merging on PPC.Hal Finkel2012-06-091-5/+5
* Don't run RAFast in the optimizing regalloc pipeline.Jakob Stoklund Olesen2012-06-0823-24/+24
* canonicalize:Nuno Lopes2012-06-081-0/+24
* Enable PPC CTR loop formation by default.Hal Finkel2012-06-082-2/+2
* Test case for r158160Manman Ren2012-06-081-0/+42
* Fix a crash in APInt::lshr when shiftAmt > BitWidth.Chad Rosier2012-06-081-0/+8
* test/CodeGen/Generic/APIntLoadStore.ll: Mark as XFAIL:ppc since r157911.NAKAMURA Takumi2012-06-081-0/+1
* Disable the PPC CTR-Loops pass by default.Hal Finkel2012-06-082-2/+2
* Fix a bug in the new PPC CTR-Loops pass.Hal Finkel2012-06-081-0/+87
* Add the PPCCTRLoops pass: a PPC machine-code-level optimization pass to form ...Hal Finkel2012-06-081-0/+78
* Revert commit 158073 while waiting for a fix. The issue is that reassociateDuncan Sands2012-06-081-0/+21
* X86: optimize generated code for integer ABSManman Ren2012-06-071-6/+10
* Fix a bug in FoldSelectOpOp. Bitcast ops may change the number of vector elem...Nadav Rotem2012-06-071-0/+11
* Use a base register instead of an index register with the local dynamic model.Rafael Espindola2012-06-071-1/+1
* Adding a missing -S to the opt invocation.Meador Inge2012-06-071-1/+1
* X86: replace SUB with CMP if possibleManman Ren2012-06-071-0/+11
* Spell optimization name correclty.Bill Wendling2012-06-061-1/+1
* Revert r157755.Manman Ren2012-06-061-11/+0
* Another testcase for r156548.Bill Wendling2012-06-061-0/+162
* Add support for dynamic stack realignment in the presence of dynamic allocas onChad Rosier2012-06-063-2/+170
* Fix combine of uno && ord -> false so that the ordering of the fcmps doesn'tChad Rosier2012-06-061-0/+10
* Grab-bag of reassociate tweaks. Unify handling of dead instructions andDuncan Sands2012-06-061-4/+6
* Correct decoder for T1 conditional B encodingRichard Barton2012-06-061-1/+10
* Remove extraneous CHECK-NOTs from previous commit and add a new test case.Chad Rosier2012-06-061-2/+10
* FileCheckize this test.Chad Rosier2012-06-061-2/+18
* Revert commit r157966Joel Jones2012-06-051-19/+0
* This change handles a another case for generating the bic instruction Joel Jones2012-06-041-0/+19
* When gvn decides to replace an instruction with another, we have to patch theRafael Espindola2012-06-044-0/+306
* Add a test case for mips64 unaligned load/store instructions.Akira Hatanaka2012-06-041-0/+73
* Rename test/CodeGen/Mips/load-shift-left-right.ll.Akira Hatanaka2012-06-041-0/+0
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