| Commit message (Collapse) | Author | Age | Files | Lines |
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It can pass two tests below on Win32.
- Clang :: CodeGenCXX/dyncast.cpp
- LLVM :: CodeGen/ARM/globals.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119023 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118829 91177308-0d34-0410-b5e6-96231b3b80d8
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post-processing after the automated encoding of an instruction.
Not yet used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118759 91177308-0d34-0410-b5e6-96231b3b80d8
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their comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118696 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118622 91177308-0d34-0410-b5e6-96231b3b80d8
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but doesn't hurt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118359 91177308-0d34-0410-b5e6-96231b3b80d8
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fixed physical registers. Start moving fp comparison
aliases to the .td file (which default to using %st1 if
nothing is specified).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118352 91177308-0d34-0410-b5e6-96231b3b80d8
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add fixed immediate values. Move the aad and aam aliases to
use this, and document it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118350 91177308-0d34-0410-b5e6-96231b3b80d8
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result instruction operand numbering matched the result pattern.
Fixing this allows us to move the xchg/test aliases to the .td file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118334 91177308-0d34-0410-b5e6-96231b3b80d8
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from c++ hacks to proper .td InstAlias definitions. Change them!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118330 91177308-0d34-0410-b5e6-96231b3b80d8
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operand list instead of the operand list redundantly declared on the alias
or instruction.
With this change, we finally remove the ins/outs list on the alias. Before:
def : InstAlias<(outs GR16:$dst), (ins GR8 :$src),
"movsx $src, $dst",
(MOVSX16rr8W GR16:$dst, GR8:$src)>;
After:
def : InstAlias<"movsx $src, $dst",
(MOVSX16rr8W GR16:$dst, GR8:$src)>;
This also makes the alias mechanism more general and powerful, which will
be exploited in subsequent patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118329 91177308-0d34-0410-b5e6-96231b3b80d8
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(someinst GR16:$foo, GR32:$foo)
Reimplement BuildAliasOperandReference to be correctly
based on the names of operands in the result pattern,
instead of on the instruction operand definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118328 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118327 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118326 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118325 91177308-0d34-0410-b5e6-96231b3b80d8
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file instead of the asmmatcher.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118324 91177308-0d34-0410-b5e6-96231b3b80d8
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and as such can be represented by an MVT - the more complicated
EVT is not needed. Use MVT for ValVT everywhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118245 91177308-0d34-0410-b5e6-96231b3b80d8
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Right now the code is partitioned but the behavior is the same.
This should be improved in the near future. This removes some
uses of TheOperandList.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118232 91177308-0d34-0410-b5e6-96231b3b80d8
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it doesn't do any lexical stuff anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118230 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118228 91177308-0d34-0410-b5e6-96231b3b80d8
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on the incoming operand list. This also makes the code simpler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118225 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118219 91177308-0d34-0410-b5e6-96231b3b80d8
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now matchables contain an explicit list of how to populate each
operand in the result instruction instead of having them somehow
magically be correlated to the input inst.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118217 91177308-0d34-0410-b5e6-96231b3b80d8
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Fixups list for the instruction so the operand encoders can add to it as
needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118206 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118190 91177308-0d34-0410-b5e6-96231b3b80d8
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value type, so there is no point in passing it around using
an EVT. Use the simpler MVT everywhere. Rather than trying
to propagate this information maximally in all the code that
using the calling convention stuff, I chose to do a mainly
low impact change instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118167 91177308-0d34-0410-b5e6-96231b3b80d8
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parts. Represent the operation mode as an optional operand instead.
rdar://8614429
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118137 91177308-0d34-0410-b5e6-96231b3b80d8
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ins/outs list that isn't specified by their asmstring. Previously
the asmmatcher would just force a 0 register into it, which clearly
isn't right. Mark a bunch of ARM instructions that use this as
isCodeGenOnly. Some of them are clearly pseudo instructions (like
t2TBB) others use a weird hasExtraSrcRegAllocReq thing that will
either need to be removed or the asmmatcher will need to be taught
about it (someday).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118119 91177308-0d34-0410-b5e6-96231b3b80d8
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that have complicated tying going on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118112 91177308-0d34-0410-b5e6-96231b3b80d8
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filling them in one at a time. Previously this iterated over the
asmoperands, which left the problem of "holes". The new approach
simplifies things.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118104 91177308-0d34-0410-b5e6-96231b3b80d8
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in the generated .inc files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118083 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118031 91177308-0d34-0410-b5e6-96231b3b80d8
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assumptions about stack layout. Specifically, LR must be saved next to FP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118026 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118025 91177308-0d34-0410-b5e6-96231b3b80d8
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merging it into a Token field in Operand, and moving the first
token to an explicit mnemonic field. These were parallel
arrays before (except for the mnemonic) which kept confusing me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118024 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117993 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117987 91177308-0d34-0410-b5e6-96231b3b80d8
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FWIW, X86 has 254 ambiguous instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117979 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117968 91177308-0d34-0410-b5e6-96231b3b80d8
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aliases installed and working. They now work when the
matched pattern and the result instruction have exactly
the same operand list.
This is now enough for us to define proper aliases for
movzx and movsx, implementing rdar://8017633 and PR7459.
Note that we do not accept instructions like:
movzx 0(%rsp), %rsi
GAS accepts this instruction, but it doesn't make any
sense because we don't know the size of the memory
operand. It could be 8/16/32 bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117901 91177308-0d34-0410-b5e6-96231b3b80d8
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represents InstAliases as well. Rename
isAssemblerInstruction -> Validate since that is what
it does (modulo the ARM $lane hack).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117899 91177308-0d34-0410-b5e6-96231b3b80d8
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instructions and InstAliases. Start creating InstructionInfo's
for Aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117898 91177308-0d34-0410-b5e6-96231b3b80d8
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in their asmstring. Fix the two x86 "NOREX" instructions that have them.
If these comments are important, the instlowering stuff can print them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117897 91177308-0d34-0410-b5e6-96231b3b80d8
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member, and make isAssemblerInstruction() a method (pushing some code
around inside it).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117895 91177308-0d34-0410-b5e6-96231b3b80d8
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todo: the result field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117894 91177308-0d34-0410-b5e6-96231b3b80d8
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CodeGenInstruction into its own helper class. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117893 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117892 91177308-0d34-0410-b5e6-96231b3b80d8
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simplify CodeGenInstruction. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117891 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117890 91177308-0d34-0410-b5e6-96231b3b80d8
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instead of strings, simplifying it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117889 91177308-0d34-0410-b5e6-96231b3b80d8
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