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* Fix a bug in tblgen that caused incorrect encodings on instructions that ↵Owen Anderson2011-04-281-1/+5
| | | | | | | | | | specified operands with "bit" instead of "bits<1>". Unfortunately, my only testcase for this is fragile, and the ARM AsmParser can't round trip the instruction in question. <rdar://problem/9345702> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130410 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a TODO.Mikhail Glushenkov2011-04-241-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130092 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused STL header includes.Jay Foad2011-04-238-10/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130068 91177308-0d34-0410-b5e6-96231b3b80d8
* Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) ↵Johnny Chen2011-04-221-0/+5
| | | | | | | | | | | should print out ldr, not ldr.n. rdar://problem/9267772 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130008 91177308-0d34-0410-b5e6-96231b3b80d8
* Define Neon load/store intrinsics for Clang as macros instead of functions.Bob Wilson2011-04-221-15/+51
| | | | | | | This is needed so the front-end can see "aligned" attributes on the type for the pointer arguments. Radar 9311427. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129964 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't allow per-register spill size and alignment.Jakob Stoklund Olesen2011-04-212-3/+0
| | | | | | | These values were not used for anything. Spill size and alignment is a property of the register class, not the register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129906 91177308-0d34-0410-b5e6-96231b3b80d8
* Prefer cheap registers for busy live ranges.Jakob Stoklund Olesen2011-04-203-3/+6
| | | | | | | | | | | | | | On the x86-64 and thumb2 targets, some registers are more expensive to encode than others in the same register class. Add a CostPerUse field to the TableGen register description, and make it available from TRI->getCostPerUse. This represents the cost of a REX prefix or a 32-bit instruction encoding required by choosing a high register. Teach the greedy register allocator to prefer cheap registers for busy live ranges (as indicated by spill weight). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129864 91177308-0d34-0410-b5e6-96231b3b80d8
* Invert the meaning of printAliasInstr's return value. It now returnsEric Christopher2011-04-181-4/+4
| | | | | | | true on success and false on failure. Update callers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129722 91177308-0d34-0410-b5e6-96231b3b80d8
* Enhance the fixed-length disassembler to support the callbacks necessary for ↵Owen Anderson2011-04-181-5/+10
| | | | | | symbolic disassembly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129708 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new bit that ImmLeaf's can opt into, which allows them to duck out ofChris Lattner2011-04-181-2/+10
| | | | | | | | | the generated FastISel. X86 doesn't need to generate code to match ADD16ri8 since ADD16ri will do just fine. This is a small codesize win in the generated instruction selector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129692 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement major new fastisel functionality: the matcher can now handle ↵Chris Lattner2011-04-182-51/+233
| | | | | | | | | | | | | | | | | | | | | | | | | immediates with value constraints on them (when defined as ImmLeaf's). This is particularly important for X86-64, where almost all reg/imm instructions take a i64immSExt32 immediate operand, which has a value constraint. Before this patch we ended up iseling the examples into such amazing code as: movabsq $7, %rax imulq %rax, %rdi movq %rdi, %rax ret now we produce: imulq $7, %rdi, %rax ret This dramatically shrinks the generated code at -O0 on x86-64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129691 91177308-0d34-0410-b5e6-96231b3b80d8
* introduce a new OpKind abstraction which wraps up operand flavors in a tidy ↵Chris Lattner2011-04-171-22/+48
| | | | | | | | | little wrapper. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129680 91177308-0d34-0410-b5e6-96231b3b80d8
* change OperandsSignature to use SmallVector<char> instead of std::vector<string>Chris Lattner2011-04-172-16/+17
| | | | | | | | since the strings are always exactly one character, and there are usually only 2-3 operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129678 91177308-0d34-0410-b5e6-96231b3b80d8
* since the VT is fixed for a ImmLeaf, there is no reason to expose it to the ↵Chris Lattner2011-04-171-2/+0
| | | | | | matching code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129677 91177308-0d34-0410-b5e6-96231b3b80d8
* now that predicates have a decent abstraction layer on them, introduce a new Chris Lattner2011-04-173-3/+26
| | | | | | | | | | kind of predicate: one that is specific to imm nodes. The predicate function specified here just checks an int64_t directly instead of messing around with SDNode's. The virtue of this is that it means that fastisel and other things can reason about these predicates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129675 91177308-0d34-0410-b5e6-96231b3b80d8
* Rework our internal representation of node predicates to expose moreChris Lattner2011-04-175-60/+139
| | | | | | | | | structure and fix some fixmes. We now have a TreePredicateFn class that handles all of the decoding of these things. This is an internal cleanup that has no impact on the code generated by tblgen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129670 91177308-0d34-0410-b5e6-96231b3b80d8
* remove some debugging code I added.Chris Lattner2011-04-171-5/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129668 91177308-0d34-0410-b5e6-96231b3b80d8
* 1. merge fast-isel-shift-imm.ll into fast-isel-x86-64.llChris Lattner2011-04-171-9/+16
| | | | | | | | | | | | 2. implement rdar://9289501 - fast isel should fold trivial multiplies to shifts 3. teach tblgen to handle shift immediates that are different sizes than the shifted operands, eliminating some code from the X86 fast isel backend. 4. Have FastISel::SelectBinaryOp use (the poorly named) FastEmit_ri_ function instead of FastEmit_ri to simplify code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129666 91177308-0d34-0410-b5e6-96231b3b80d8
* Initial work to improve documentation for Clang's diagnostics, from Matthieu ↵Douglas Gregor2011-04-153-3/+74
| | | | | | Monrocq git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129613 91177308-0d34-0410-b5e6-96231b3b80d8
* Increase SubtargetFeatureKV Value and Implies fields to 64 bits since some ↵Evan Cheng2011-04-151-6/+12
| | | | | | targets are getting very close to 32 subtarget features. Also teach tablegen to error when there are more than 64 features to guard against undefined behavior. rdar://9282332 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129590 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a ton of comment typos found by codespell. Patch byChris Lattner2011-04-1513-22/+22
| | | | | | | | Luis Felipe Strano Moraes! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129558 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an option to not print the alias of an instruction. It defaults to "printBill Wendling2011-04-131-0/+2
| | | | | | | the alias". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129485 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb disassembler was erroneously rejecting "blx sp" instruction.Johnny Chen2011-04-111-0/+4
| | | | | | | rdar://problem/9267838 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129320 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen: Keep the order of DECL_CONTEXT() for DeclNodes.td. RecordVector ↵NAKAMURA Takumi2011-04-111-4/+7
| | | | | | | | may be used instead of RecordSet. The result of DeclNodes.inc was unstable on msys, Windows 7 x64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129317 91177308-0d34-0410-b5e6-96231b3b80d8
* build: Add support for a SHOW_DIAGNOSTICS build variable.Daniel Dunbar2011-04-111-0/+52
| | | | | | | | | If enabled, this will attempt to use the CC_LOG_DIAGNOSTICS feature I dropped into Clang to print a log of all the diagnostics generated during an individual build (from the top-level). Not sure if this will actually be useful, but for now it is handy for testing the option. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129312 91177308-0d34-0410-b5e6-96231b3b80d8
* fix PR9629 - We were lowering regexes like a{{b|c}}d into ab|cd, whichChris Lattner2011-04-091-0/+8
| | | | | | | | | is substantially different than a(b|c)d. Form the latter regex instead. This found a few problems in the testsuite, which serves as its test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129196 91177308-0d34-0410-b5e6-96231b3b80d8
* various cleanups, no functionality change.Chris Lattner2011-04-091-10/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129192 91177308-0d34-0410-b5e6-96231b3b80d8
* Only emit the AvailableFeatures variable if it's used.Bill Wendling2011-04-081-4/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129124 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace the old algorithm that emitted the "print the alias for an instruction"Bill Wendling2011-04-071-146/+59
| | | | | | | | | | | | | | with the newer, cleaner model. It uses the IAPrinter class to hold the information that is needed to match an instruction with its alias. This also takes into account the available features of the platform. There is one bit of ugliness. The way the logic determines if a pattern is unique is O(N**2), which is gross. But in reality, the number of items it's checking against isn't large. So while it's N**2, it shouldn't be a massive time sink. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129110 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for the VIA PadLock instructions.Joerg Sonnenberger2011-04-044-10/+31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128826 91177308-0d34-0410-b5e6-96231b3b80d8
* Use array_lengthofJoerg Sonnenberger2011-04-041-2/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128823 91177308-0d34-0410-b5e6-96231b3b80d8
* Change loops to derive the number of tables automaticallyJoerg Sonnenberger2011-04-041-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128818 91177308-0d34-0410-b5e6-96231b3b80d8
* tlbgen/MC: StringRef's to temporary objects considered harmful.Daniel Dunbar2011-04-011-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128735 91177308-0d34-0410-b5e6-96231b3b80d8
* Add annotations to tablegen-generated processor itineraries, or replace them ↵Andrew Trick2011-04-012-16/+21
| | | | | | with something meaningful. I want to be able to read and debug the generated tables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128703 91177308-0d34-0410-b5e6-96231b3b80d8
* whitespaceAndrew Trick2011-04-012-68/+68
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128701 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix typo in generated HTML.Nick Lewycky2011-03-311-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128594 91177308-0d34-0410-b5e6-96231b3b80d8
* Use intrinsics for Neon vmull operations. Radar 9208957.Bob Wilson2011-03-312-27/+17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128591 91177308-0d34-0410-b5e6-96231b3b80d8
* ClangSAEmClangSACheckersEmitter, emit info about groups.Argyrios Kyrtzidis2011-03-301-64/+79
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128515 91177308-0d34-0410-b5e6-96231b3b80d8
* Quiet a gcc warning about changed name lookup rulesMatt Beaumont-Gay2011-03-291-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128497 91177308-0d34-0410-b5e6-96231b3b80d8
* In ClangSACheckersEmitter:Argyrios Kyrtzidis2011-03-291-7/+61
| | | | | | | | - Also emit a list of packages and groups sorted by name - Avoid iterating over DenseSet so that the output of the arrays is deterministic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128489 91177308-0d34-0410-b5e6-96231b3b80d8
* For ClangSACheckersEmitter, allow a package to belong to checker group, in ↵Argyrios Kyrtzidis2011-03-291-8/+28
| | | | | | which all its checkers will go into the group. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128474 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove scripts used by TEST=dbg from here. They now live inside llvm test suite.Devang Patel2011-03-282-364/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128425 91177308-0d34-0410-b5e6-96231b3b80d8
* Partially revert commit 127155: I think it is much more convenientDuncan Sands2011-03-271-9/+26
| | | | | | | | to have structured log files rather than one big file produced by piping output. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128378 91177308-0d34-0410-b5e6-96231b3b80d8
* Extend Clang's TableGen emitter for attributes to support bool arguments.Douglas Gregor2011-03-261-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128330 91177308-0d34-0410-b5e6-96231b3b80d8
* Useful script for finding regressions in the nightly testsuite.Duncan Sands2011-03-251-0/+130
| | | | | | | I think it was written by Pawel Worach. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128268 91177308-0d34-0410-b5e6-96231b3b80d8
* delegate the disassembly of t2ADR to the more generic t2ADDri12/t2SUBri12 ↵Johnny Chen2011-03-251-0/+5
| | | | | | instructions, and add a test case for that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128249 91177308-0d34-0410-b5e6-96231b3b80d8
* The opcode names ("tLDM", "tLDM_UPD") used for conflict resolution have been ↵Johnny Chen2011-03-241-2/+2
| | | | | | | | | | stale since the change to ("tLDMIA", "tLDMIA_UPD"). Update the conflict resolution code and add test cases for that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128247 91177308-0d34-0410-b5e6-96231b3b80d8
* The ARM disassembler was confused with the 16-bit tSTMIA instruction.Johnny Chen2011-03-241-0/+5
| | | | | | | | According to A8.6.189 STM/STMIA/STMEA (Encoding T1), there's only tSTMIA_UPD available. Ignore tSTMIA for the decoder emitter and add a test case for that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128246 91177308-0d34-0410-b5e6-96231b3b80d8
* Add asm parsing support w/ testcases for strex/ldrex family of instructionsBruno Cardoso Lopes2011-03-241-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128236 91177308-0d34-0410-b5e6-96231b3b80d8
* ADR was added with the wrong encoding for inst{24-21}, and the ARM decoder ↵Johnny Chen2011-03-241-0/+4
| | | | | | | | | | was fooled. Set the encoding bits to {0,?,?,0}, not 0. Plus delegate the disassembly of ADR to the more generic ADDri/SUBri instructions, and add a test case for that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128234 91177308-0d34-0410-b5e6-96231b3b80d8
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