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| author | Marek Olšák <marek.olsak@amd.com> | 2016-10-10 18:51:24 +0200 |
|---|---|---|
| committer | Marek Olšák <marek.olsak@amd.com> | 2016-10-12 18:29:40 +0200 |
| commit | 40e1f7e09bf1bc9b8ed6f847562bbb7154025420 (patch) | |
| tree | 914d8dab62758e5488cda94e215804aee916cc23 /src/gallium/drivers/radeonsi/si_state.c | |
| parent | 8cdce30cc20983dcb971dd906a9a9007e282081d (diff) | |
| download | external_mesa3d-40e1f7e09bf1bc9b8ed6f847562bbb7154025420.zip external_mesa3d-40e1f7e09bf1bc9b8ed6f847562bbb7154025420.tar.gz external_mesa3d-40e1f7e09bf1bc9b8ed6f847562bbb7154025420.tar.bz2 | |
radeonsi: use TC write-back instead of full cache invalidation
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_state.c')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state.c | 12 |
1 files changed, 3 insertions, 9 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 34f3ed7..ad65fc2 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -3397,21 +3397,15 @@ static void si_memory_barrier(struct pipe_context *ctx, unsigned flags) * L1 isn't used. */ if (sctx->screen->b.chip_class <= CIK) - sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2; + sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2; } if (flags & PIPE_BARRIER_FRAMEBUFFER) sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER; if (flags & (PIPE_BARRIER_FRAMEBUFFER | - PIPE_BARRIER_INDIRECT_BUFFER)) { - /* Not sure if INV_GLOBAL_L2 is the best thing here. - * - * We need to make sure that TC L1 & L2 are written back to - * memory, because CB fetches don't consider TC, but there's - * no need to invalidate any TC cache lines. */ - sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2; - } + PIPE_BARRIER_INDIRECT_BUFFER)) + sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2; } static void *si_create_blend_custom(struct si_context *sctx, unsigned mode) |