gallium/radeon: drop support for LLVM 3.5

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

v2: adjust the comment in the amdgpu winsys

3 files changed, 7 insertions, 78 deletions

diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c
index 4d27e86..7370a11 100644
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -45,12 +45,6 @@ struct si_compute {
 
 	struct r600_resource *input_buffer;
 	struct pipe_resource *global_buffers[MAX_GLOBAL_BUFFERS];
-
-#if HAVE_LLVM < 0x0306
-	unsigned num_kernels;
-	struct si_shader *kernels;
-	LLVMContextRef llvm_ctx;
-#endif
 };
 
 static void init_scratch_buffer(struct si_context *sctx, struct si_compute *program)
@@ -111,29 +105,6 @@ static void *si_create_compute_state(
 	program->private_size = cso->req_private_mem;
 	program->input_size = cso->req_input_mem;
 
-#if HAVE_LLVM < 0x0306
-	{
-		unsigned i;
-		program->llvm_ctx = LLVMContextCreate();
-	        program->num_kernels = radeon_llvm_get_num_kernels(program->llvm_ctx,
-					code, header->num_bytes);
-	        program->kernels = CALLOC(sizeof(struct si_shader),
-                                                        program->num_kernels);
-	        for (i = 0; i < program->num_kernels; i++) {
-		        LLVMModuleRef mod = radeon_llvm_get_kernel_module(program->llvm_ctx, i,
-                                                        code, header->num_bytes);
-			si_compile_llvm(sctx->screen, &program->kernels[i].binary,
-					&program->kernels[i].config, sctx->tm,
-					mod, &sctx->b.debug, TGSI_PROCESSOR_COMPUTE,
-					"Compute Shader");
-			si_shader_dump(sctx->screen, &program->kernels[i],
-				       &sctx->b.debug, TGSI_PROCESSOR_COMPUTE);
-			si_shader_binary_upload(sctx->screen, &program->kernels[i]);
-			LLVMDisposeModule(mod);
-		}
-	}
-#else
-
 	radeon_elf_read(code, header->num_bytes, &program->shader.binary);
 
 	/* init_scratch_buffer patches the shader code with the scratch address,
@@ -147,7 +118,6 @@ static void *si_create_compute_state(
 		       TGSI_PROCESSOR_COMPUTE);
 	si_shader_binary_upload(sctx->screen, &program->shader);
 
-#endif
 	program->input_buffer =	si_resource_create_custom(sctx->b.b.screen,
 		PIPE_USAGE_IMMUTABLE, program->input_size);
 
@@ -247,11 +217,6 @@ static void si_launch_grid(
 	unsigned lds_blocks;
 	unsigned num_waves_for_scratch;
 
-#if HAVE_LLVM < 0x0306
-	shader = &program->kernels[pc];
-#endif
-
-
 	radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0) | PKT3_SHADER_TYPE_S(1));
 	radeon_emit(cs, 0x80000000);
 	radeon_emit(cs, 0x80000000);
@@ -266,10 +231,8 @@ static void si_launch_grid(
 
 	pm4->compute_pkt = true;
 
-#if HAVE_LLVM >= 0x0306
 	/* Read the config information */
 	si_shader_binary_read_config(&shader->binary, &shader->config, pc);
-#endif
 
 	/* Upload the kernel arguments */
 
@@ -360,10 +323,8 @@ static void si_launch_grid(
 	}
 
 	shader_va = shader->bo->gpu_address;
-
-#if HAVE_LLVM >= 0x0306
 	shader_va += pc;
-#endif
+
 	radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, shader->bo,
 				  RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
 	si_pm4_set_reg(pm4, R_00B830_COMPUTE_PGM_LO, shader_va >> 8);
@@ -448,26 +409,9 @@ static void si_delete_compute_state(struct pipe_context *ctx, void* state){
 		return;
 	}
 
-#if HAVE_LLVM < 0x0306
-	if (program->kernels) {
-		for (int i = 0; i < program->num_kernels; i++){
-			if (program->kernels[i].bo){
-				si_shader_destroy(&program->kernels[i]);
-			}
-		}
-		FREE(program->kernels);
-	}
-
-	if (program->llvm_ctx){
-		LLVMContextDispose(program->llvm_ctx);
-	}
-#else
 	si_shader_destroy(&program->shader);
-#endif
-
 	pipe_resource_reference(
 		(struct pipe_resource **)&program->input_buffer, NULL);
-
 	FREE(program);
 }
 
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index 61ce976..e9d69d2 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -74,9 +74,7 @@ static void si_destroy_context(struct pipe_context *context)
 
 	r600_common_context_cleanup(&sctx->b);
 
-#if HAVE_LLVM >= 0x0306
 	LLVMDisposeTargetMachine(sctx->tm);
-#endif
 
 	r600_resource_reference(&sctx->trace_buf, NULL);
 	r600_resource_reference(&sctx->last_trace_buf, NULL);
@@ -104,9 +102,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
 	struct si_screen* sscreen = (struct si_screen *)screen;
 	struct radeon_winsys *ws = sscreen->b.ws;
 	LLVMTargetRef r600_target;
-#if HAVE_LLVM >= 0x0306
 	const char *triple = "amdgcn--";
-#endif
 	int shader, i;
 
 	if (!sctx)
@@ -210,7 +206,6 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
 	 */
 	sctx->scratch_waves = 32 * sscreen->b.info.num_good_compute_units;
 
-#if HAVE_LLVM >= 0x0306
 	/* Initialize LLVM TargetMachine */
 	r600_target = radeon_llvm_get_r600_target(triple);
 	sctx->tm = LLVMCreateTargetMachine(r600_target, triple,
@@ -223,7 +218,6 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
 					   LLVMCodeGenLevelDefault,
 					   LLVMRelocDefault,
 					   LLVMCodeModelDefault);
-#endif
 
 	return &sctx->b.b;
 fail:
@@ -310,6 +304,7 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 	case PIPE_CAP_INVALIDATE_BUFFER:
 	case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 	case PIPE_CAP_QUERY_MEMORY_INFO:
+	case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 		return 1;
 
 	case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
@@ -335,9 +330,6 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 	case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 		return 4;
 
-	case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
-		return HAVE_LLVM >= 0x0306;
-
 	case PIPE_CAP_GLSL_FEATURE_LEVEL:
 		return HAVE_LLVM >= 0x0307 ? 410 : 330;
 
@@ -449,18 +441,13 @@ static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enu
 	case PIPE_SHADER_TESS_CTRL:
 	case PIPE_SHADER_TESS_EVAL:
 		/* LLVM 3.6.2 is required for tessellation because of bug fixes there */
-		if (HAVE_LLVM < 0x0306 ||
-		    (HAVE_LLVM == 0x0306 && MESA_LLVM_VERSION_PATCH < 2))
+		if (HAVE_LLVM == 0x0306 && MESA_LLVM_VERSION_PATCH < 2)
 			return 0;
 		break;
 	case PIPE_SHADER_COMPUTE:
 		switch (param) {
 		case PIPE_SHADER_CAP_PREFERRED_IR:
-#if HAVE_LLVM < 0x0306
-			return PIPE_SHADER_IR_LLVM;
-#else
 			return PIPE_SHADER_IR_NATIVE;
-#endif
 		case PIPE_SHADER_CAP_DOUBLES:
 			return HAVE_LLVM >= 0x0307;
 
diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index 01f1e48..baa1090 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -4374,12 +4374,10 @@ static void si_init_shader_ctx(struct si_shader_context *ctx,
 	bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
 	bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
 
-	if (HAVE_LLVM >= 0x0306) {
-		bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
-		bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.maxnum.f32";
-		bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
-		bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.minnum.f32";
-	}
+	bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
+	bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.maxnum.f32";
+	bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
+	bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.minnum.f32";
 }
 
 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,