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authorMarek Olšák <marek.olsak@amd.com>2015-09-10 18:27:53 +0200
committerMarek Olšák <marek.olsak@amd.com>2015-09-24 19:51:43 +0200
commit263f5a2cf97e455e48dbd7728cb0ac10fd699746 (patch)
tree4a0c85caec3ef31a3a655c334da54ec492872076 /src/gallium
parent22d3ccf5a814bfc768e373d0c983a356f4e4efe3 (diff)
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radeonsi: skip drawing if GS ring allocations fail
Cc: 11.0 <mesa-stable@lists.freedesktop.org> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Diffstat (limited to 'src/gallium')
-rw-r--r--src/gallium/drivers/radeonsi/si_state_shaders.c11
1 files changed, 10 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 11b58e8..bc7fdb3 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -1069,9 +1069,15 @@ static void si_init_gs_rings(struct si_context *sctx)
sctx->esgs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
PIPE_USAGE_DEFAULT, esgs_ring_size);
+ if (!sctx->esgs_ring)
+ return;
sctx->gsvs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
PIPE_USAGE_DEFAULT, gsvs_ring_size);
+ if (!sctx->gsvs_ring) {
+ pipe_resource_reference(&sctx->esgs_ring, NULL);
+ return;
+ }
/* Append these registers to the init config state. */
if (sctx->b.chip_class >= CIK) {
@@ -1443,8 +1449,11 @@ bool si_update_shaders(struct si_context *sctx)
si_pm4_bind_state(sctx, vs, sctx->gs_shader->current->gs_copy_shader->pm4);
si_update_so(sctx, sctx->gs_shader);
- if (!sctx->gsvs_ring)
+ if (!sctx->gsvs_ring) {
si_init_gs_rings(sctx);
+ if (!sctx->gsvs_ring)
+ return false;
+ }
si_update_gs_rings(sctx);
} else {