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author | Jason Ekstrand <jason.ekstrand@intel.com> | 2016-04-21 16:39:56 -0700 |
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committer | Jason Ekstrand <jason.ekstrand@intel.com> | 2016-04-26 14:55:22 -0700 |
commit | b6dd8e42f09d98a536a38c33383238ec3595d066 (patch) | |
tree | 26ef417d61353d02bc64acc85fa3daf610606ad8 /src/mesa/drivers/dri/i965/brw_blorp.h | |
parent | a543f741bf33e4632d4d43b797bdcd0e04c7983f (diff) | |
download | external_mesa3d-b6dd8e42f09d98a536a38c33383238ec3595d066.zip external_mesa3d-b6dd8e42f09d98a536a38c33383238ec3595d066.tar.gz external_mesa3d-b6dd8e42f09d98a536a38c33383238ec3595d066.tar.bz2 |
i965/blorp: Turn blorp_surface_info into a C-style struct
This commit is mostly mechanical except that it changes where we set the
swizzle. Previously, the blorp_surface_info constructor defaulted the
swizzle to SWIZZLE_XYZW. Now, we memset to zero and fill out the swizzle
when we setup the rest of the struct.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_blorp.h')
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_blorp.h | 32 |
1 files changed, 17 insertions, 15 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h b/src/mesa/drivers/dri/i965/brw_blorp.h index 191ccbb..f4f7f7a 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.h +++ b/src/mesa/drivers/dri/i965/brw_blorp.h @@ -69,18 +69,8 @@ enum { BRW_BLORP_NUM_BINDING_TABLE_ENTRIES }; -class brw_blorp_surface_info +struct brw_blorp_surface_info { -public: - brw_blorp_surface_info(); - - void set(struct brw_context *brw, - struct intel_mipmap_tree *mt, - unsigned int level, unsigned int layer, - mesa_format format, bool is_render_target); - - uint32_t compute_tile_offsets(uint32_t *tile_x, uint32_t *tile_y) const; - struct intel_mipmap_tree *mt; /** @@ -161,7 +151,7 @@ public: * For MSAA surfaces, MSAA layout that should be used when setting up the * surface state for this surface. */ - intel_msaa_layout msaa_layout; + enum intel_msaa_layout msaa_layout; /** * In order to support cases where RGBA format is backing client requested @@ -172,6 +162,18 @@ public: int swizzle; }; +void +brw_blorp_surface_info_init(struct brw_context *brw, + struct brw_blorp_surface_info *info, + struct intel_mipmap_tree *mt, + unsigned int level, unsigned int layer, + mesa_format format, bool is_render_target); + +uint32_t +brw_blorp_compute_tile_offsets(const struct brw_blorp_surface_info *info, + uint32_t *tile_x, uint32_t *tile_y); + + struct brw_blorp_coord_transform_params { @@ -228,10 +230,10 @@ public: uint32_t y0; uint32_t x1; uint32_t y1; - brw_blorp_surface_info depth; + struct brw_blorp_surface_info depth; uint32_t depth_format; - brw_blorp_surface_info src; - brw_blorp_surface_info dst; + struct brw_blorp_surface_info src; + struct brw_blorp_surface_info dst; enum gen6_hiz_op hiz_op; unsigned fast_clear_op; bool color_write_disable[4]; |