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| author | Kenneth Graunke <kenneth@whitecape.org> | 2015-12-24 13:09:26 -0800 |
|---|---|---|
| committer | Kenneth Graunke <kenneth@whitecape.org> | 2015-12-28 13:17:03 -0800 |
| commit | bd8ab8dedb2cc557ea3cb58d507f237743b3f7f9 (patch) | |
| tree | 4c5c4b0a081890f90920be3f0f89fa6151f0a141 /src/mesa/drivers/dri/i965/brw_defines.h | |
| parent | b7793783b3df94880655234bc2a9054eddf01913 (diff) | |
| download | external_mesa3d-bd8ab8dedb2cc557ea3cb58d507f237743b3f7f9.zip external_mesa3d-bd8ab8dedb2cc557ea3cb58d507f237743b3f7f9.tar.gz external_mesa3d-bd8ab8dedb2cc557ea3cb58d507f237743b3f7f9.tar.bz2 | |
i965: Don't set interleave or complete on TCS EOT message.
Setting interleave on the TCS EOT message causes Ivybridge hardware to
GPU hang like crazy. Individual tests would pass, but running even a
simple test like nop.shader_test in a loop would hang within 1-3 runs.
Adding sleep delays worked around the problem, somehow.
Interleave doesn't make much sense given that we only have one patch
URB handle, not two. Complete doesn't seem useful either.
There's no reason to actually set those bits. We were just being lazy.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_defines.h')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_defines.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index d013748..10a6d39 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -1315,6 +1315,7 @@ enum opcode { TCS_OPCODE_CREATE_BARRIER_HEADER, TCS_OPCODE_SRC0_010_IS_ZERO, TCS_OPCODE_RELEASE_INPUT, + TCS_OPCODE_THREAD_END, TES_OPCODE_GET_PRIMITIVE_ID, TES_OPCODE_CREATE_INPUT_READ_HEADER, |