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| author | Ben Widawsky <benjamin.widawsky@intel.com> | 2015-05-15 21:25:36 -0700 |
|---|---|---|
| committer | Ben Widawsky <benjamin.widawsky@intel.com> | 2015-05-18 12:02:18 -0700 |
| commit | c14bb072301f68b68dcc9fff3e49210cb0819912 (patch) | |
| tree | 3043989bf8163848d36892790ef875b38761a0ef /src/mesa/drivers/dri/i965/brw_defines.h | |
| parent | 313abbb8ca1f41b28c58571ca8217332d52283c7 (diff) | |
| download | external_mesa3d-c14bb072301f68b68dcc9fff3e49210cb0819912.zip external_mesa3d-c14bb072301f68b68dcc9fff3e49210cb0819912.tar.gz external_mesa3d-c14bb072301f68b68dcc9fff3e49210cb0819912.tar.bz2 | |
i965: Add Gen9 surface state decoding
Gen9 surface state is very similar to the previous generation. The important
changes here are aux mode, and the way clear colors work.
NOTE: There are some things intentionally left out of this decoding.
v2: Redo the string for the aux buffer type to address compressed variants.
v3: Use the shift for compression enable (instead of compression mode) (Topi)
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_defines.h')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_defines.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 8fd5a49..dedc381 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -608,6 +608,8 @@ #define GEN8_SURFACE_AUX_MODE_HIZ 3 /* Surface state DW7 */ +#define GEN9_SURFACE_RT_COMPRESSION_SHIFT 30 +#define GEN9_SURFACE_RT_COMPRESSION_MASK INTEL_MASK(30, 30) #define GEN7_SURFACE_CLEAR_COLOR_SHIFT 28 #define GEN7_SURFACE_SCS_R_SHIFT 25 #define GEN7_SURFACE_SCS_R_MASK INTEL_MASK(27, 25) |