diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2013-08-12 16:07:08 +0300 |
|---|---|---|
| committer | Chad Versace <chad.versace@linux.intel.com> | 2013-08-21 10:14:04 -0700 |
| commit | e6893b99adcd6d9fb1bd49067883f66cc5603fe7 (patch) | |
| tree | 911dcf8c97d0cfb929ac509216f5f4a6aa149c2c /src/mesa/drivers/dri/i965/brw_draw_upload.c | |
| parent | 22161983c38fe19b393e5b983f4945dc527ccb1b (diff) | |
| download | external_mesa3d-e6893b99adcd6d9fb1bd49067883f66cc5603fe7.zip external_mesa3d-e6893b99adcd6d9fb1bd49067883f66cc5603fe7.tar.gz external_mesa3d-e6893b99adcd6d9fb1bd49067883f66cc5603fe7.tar.bz2 | |
i965/gen7: Set MOCS L3 cacheability for IVB/BYT (v2)
IVB/BYT also has the same L3 cacheability control in MOCS as HSW,
so let's make use of it.
pts/xonotic and pts/reaction @ 1920x1080 gain ~4% on my IVB GT2. Most
other things show less gains/no regressions, except furmark which
loses some 10 points.
I didn't have a BYT at hand for testing.
v2: Don't check (brw->gen == 7) in gen7 functions. (chadv)
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_draw_upload.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_draw_upload.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index 158c9e5..390b4a3 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -659,7 +659,7 @@ static void brw_emit_vertices(struct brw_context *brw) if (brw->gen >= 7) dw0 |= GEN7_VB0_ADDRESS_MODIFYENABLE; - if (brw->is_haswell) + if (brw->gen == 7) dw0 |= GEN7_MOCS_L3 << 16; OUT_BATCH(dw0 | (buffer->stride << BRW_VB0_PITCH_SHIFT)); |