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| author | Kristian Høgsberg <krh@bitplanet.net> | 2014-10-20 23:05:09 -0700 |
|---|---|---|
| committer | Kristian Høgsberg <krh@bitplanet.net> | 2014-12-10 12:29:04 -0800 |
| commit | c5b3878714a75dab40439622050b2ce6f60337c0 (patch) | |
| tree | 869545b0693e5ed463edb206c54cd3f8935f2e31 /src/mesa/drivers/dri/i965/brw_gs_surface_state.c | |
| parent | d9e29f5d88d2ddd8ee9d10b7d88377a60fd0094f (diff) | |
| download | external_mesa3d-c5b3878714a75dab40439622050b2ce6f60337c0.zip external_mesa3d-c5b3878714a75dab40439622050b2ce6f60337c0.tar.gz external_mesa3d-c5b3878714a75dab40439622050b2ce6f60337c0.tar.bz2 | |
i965: Add new SIMD8 VS prog data flag
This flag signals that we have a SIMD8 VS shader so we can set up the
corresponding state accordingly. This boils down to setting
the BDW+ SIMD8 enable bit in 3DSTATE_VS and making UBO and pull
constant buffers use dword pitch.
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_gs_surface_state.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_gs_surface_state.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_gs_surface_state.c b/src/mesa/drivers/dri/i965/brw_gs_surface_state.c index 00fcc31..a323e4d 100644 --- a/src/mesa/drivers/dri/i965/brw_gs_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_gs_surface_state.c @@ -78,7 +78,7 @@ brw_upload_gs_ubo_surfaces(struct brw_context *brw) /* BRW_NEW_GS_PROG_DATA */ brw_upload_ubo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_GEOMETRY], - &brw->gs.base, &brw->gs.prog_data->base.base); + &brw->gs.base, &brw->gs.prog_data->base.base, false); } const struct brw_tracked_state brw_gs_ubo_surfaces = { |