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authorMatt Turner <mattst88@gmail.com>2016-02-14 23:21:03 -0800
committerMatt Turner <mattst88@gmail.com>2016-03-30 19:54:30 -0700
commit0d253ce34a8074a6c880d405c5bf860766afe358 (patch)
treef8f2b1ac307f1165376368725b1747a3bc314ab1 /src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
parent65bc94022b0fd31d01c8de65f7f1115a86baa65a (diff)
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i965: Simplify full scheduling-barrier conditions.
All of these were simply code for "architecture register file" (and in the case of destinations, "not the null register"). Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp')
-rw-r--r--src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp35
1 files changed, 8 insertions, 27 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
index 51d9ce1..2153898 100644
--- a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
+++ b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
@@ -964,10 +964,7 @@ fs_instruction_scheduler::calculate_deps()
}
} else if (inst->src[i].is_accumulator()) {
add_dep(last_accumulator_write, n);
- } else if (inst->src[i].file != BAD_FILE &&
- inst->src[i].file != IMM &&
- inst->src[i].file != UNIFORM) {
- assert(inst->src[i].file != MRF);
+ } else if (inst->src[i].file == ARF) {
add_barrier_deps(n);
}
}
@@ -1026,8 +1023,7 @@ fs_instruction_scheduler::calculate_deps()
} else if (inst->dst.is_accumulator()) {
add_dep(last_accumulator_write, n);
last_accumulator_write = n;
- } else if (inst->dst.file != BAD_FILE &&
- !inst->dst.is_null()) {
+ } else if (inst->dst.file == ARF && !inst->dst.is_null()) {
add_barrier_deps(n);
}
@@ -1080,10 +1076,7 @@ fs_instruction_scheduler::calculate_deps()
}
} else if (inst->src[i].is_accumulator()) {
add_dep(n, last_accumulator_write, 0);
- } else if (inst->src[i].file != BAD_FILE &&
- inst->src[i].file != IMM &&
- inst->src[i].file != UNIFORM) {
- assert(inst->src[i].file != MRF);
+ } else if (inst->src[i].file == ARF) {
add_barrier_deps(n);
}
}
@@ -1140,8 +1133,7 @@ fs_instruction_scheduler::calculate_deps()
}
} else if (inst->dst.is_accumulator()) {
last_accumulator_write = n;
- } else if (inst->dst.file != BAD_FILE &&
- !inst->dst.is_null()) {
+ } else if (inst->dst.file == ARF && !inst->dst.is_null()) {
add_barrier_deps(n);
}
@@ -1204,12 +1196,7 @@ vec4_instruction_scheduler::calculate_deps()
} else if (inst->src[i].is_accumulator()) {
assert(last_accumulator_write);
add_dep(last_accumulator_write, n);
- } else if (inst->src[i].file != BAD_FILE &&
- inst->src[i].file != IMM &&
- inst->src[i].file != UNIFORM) {
- /* No reads from MRF, and ATTR is already translated away */
- assert(inst->src[i].file != MRF &&
- inst->src[i].file != ATTR);
+ } else if (inst->src[i].file == ARF) {
add_barrier_deps(n);
}
}
@@ -1248,8 +1235,7 @@ vec4_instruction_scheduler::calculate_deps()
} else if (inst->dst.is_accumulator()) {
add_dep(last_accumulator_write, n);
last_accumulator_write = n;
- } else if (inst->dst.file != BAD_FILE &&
- !inst->dst.is_null()) {
+ } else if (inst->dst.file == ARF && !inst->dst.is_null()) {
add_barrier_deps(n);
}
@@ -1291,11 +1277,7 @@ vec4_instruction_scheduler::calculate_deps()
add_dep(n, last_fixed_grf_write);
} else if (inst->src[i].is_accumulator()) {
add_dep(n, last_accumulator_write);
- } else if (inst->src[i].file != BAD_FILE &&
- inst->src[i].file != IMM &&
- inst->src[i].file != UNIFORM) {
- assert(inst->src[i].file != MRF &&
- inst->src[i].file != ATTR);
+ } else if (inst->src[i].file == ARF) {
add_barrier_deps(n);
}
}
@@ -1330,8 +1312,7 @@ vec4_instruction_scheduler::calculate_deps()
last_fixed_grf_write = n;
} else if (inst->dst.is_accumulator()) {
last_accumulator_write = n;
- } else if (inst->dst.file != BAD_FILE &&
- !inst->dst.is_null()) {
+ } else if (inst->dst.file == ARF && !inst->dst.is_null()) {
add_barrier_deps(n);
}