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authorJason Ekstrand <jason.ekstrand@intel.com>2015-11-23 21:39:15 -0800
committerJason Ekstrand <jason.ekstrand@intel.com>2016-04-15 14:04:38 -0700
commitaaac8a18904f44e93a2223c93727086358d6a655 (patch)
tree6ffa782045c9f78180e704e81058e9278297e469 /src/mesa/drivers/dri/i965/brw_vec4.cpp
parent61ee5e62a2beeb2e405ff3aa5e3eb26d1bf5437d (diff)
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i965/vec4: Add support for SHADER_OPCODE_MOV_INDIRECT
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_vec4.cpp')
-rw-r--r--src/mesa/drivers/dri/i965/brw_vec4.cpp1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 87b5ff9..e2aa109 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -251,6 +251,7 @@ vec4_instruction::can_do_writemask(const struct brw_device_info *devinfo)
case TES_OPCODE_CREATE_INPUT_READ_HEADER:
case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
case VEC4_OPCODE_URB_READ:
+ case SHADER_OPCODE_MOV_INDIRECT:
return false;
default:
/* The MATH instruction on Gen6 only executes in align1 mode, which does