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| author | Eric Anholt <eric@anholt.net> | 2011-11-17 14:45:54 -0800 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2011-11-29 16:44:51 -0800 |
| commit | d84a180417d1eabd680554970f1eaaa93abcd41e (patch) | |
| tree | aa01f69e18c3abc523aa0ed60fa8289a4deac8ab /src/mesa/drivers/dri/i965/gen7_sf_state.c | |
| parent | ccd4d4367f2b4e5aebfc59b832599812a4a1c7d8 (diff) | |
| download | external_mesa3d-d84a180417d1eabd680554970f1eaaa93abcd41e.zip external_mesa3d-d84a180417d1eabd680554970f1eaaa93abcd41e.tar.gz external_mesa3d-d84a180417d1eabd680554970f1eaaa93abcd41e.tar.bz2 | |
i965: Base HW depth format setup based on MESA_FORMAT, not bpp.
This will make handling new formats (like actually exposing Z32F)
easier and more reliable.
v2: Remove the check for hiz buffer -- the MESA_FORMAT should really
be giving us the value we want even for hiz.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src/mesa/drivers/dri/i965/gen7_sf_state.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen7_sf_state.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/gen7_sf_state.c b/src/mesa/drivers/dri/i965/gen7_sf_state.c index d3ffbd3..8876722 100644 --- a/src/mesa/drivers/dri/i965/gen7_sf_state.c +++ b/src/mesa/drivers/dri/i965/gen7_sf_state.c @@ -154,7 +154,7 @@ upload_sf_state(struct brw_context *brw) dw1 = GEN6_SF_STATISTICS_ENABLE | GEN6_SF_VIEWPORT_TRANSFORM_ENABLE; /* _NEW_BUFFERS */ - dw1 |= (gen7_depth_format(brw) << GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT); + dw1 |= (brw_depthbuffer_format(brw) << GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT); /* _NEW_POLYGON */ if ((ctx->Polygon.FrontFace == GL_CCW) ^ render_to_fbo) |