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path: root/src/intel/vulkan/gen8_cmd_buffer.c
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* anv/gen8: Stall when needed in Cmd(Set|Reset)EventJason Ekstrand2016-11-231-0/+29
| | | | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Chad Versace <chadversary@chromium.org> Cc: "13.0" <mesa-stable@lists.freedesktop.org> (cherry picked from commit 71397042fea36a2a14b530b75829ad13f969fd00)
* anv/cmd_buffer: Unify flush_compute_state across gensJason Ekstrand2016-10-171-87/+0
| | | | | | | | | With one small genxml change, the two versions were basically identical. The only differences were one #define for HSW+ and a field that is missing on Haswell but exists everywhere else. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
* anv/hiz: Perform HiZ resolves for all partial rendersJason Ekstrand2016-10-141-1/+11
| | | | | | | | | | | | | | If we don't, we can end up with corruption in the portion of the depth buffer that lies outside the render area when we do a HiZ resolve at the end. The only reason we weren't seeing this before was that all of the meta-based clears such as VkCmdClearDepthStencilImage were internally using HiZ so the HiZ buffer never truly got out-of-sync. If the CTS ever tested a depth upload (which doesn't care about HiZ) and then a partial render we would have seen problems. Soon, we will be using blorp to do depth clears and it won't bother with HiZ so we would get CTS regressions without this. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
* anv/cmd_buffer: Enable rendering to HiZChad Versace2016-10-071-0/+4
| | | | | | | | | | | | | | | | | | | | | Nanley Chery: (rebase) - Resolve conflicts with new anv_batch_emit macro (amend) - Handle a QPitch TODO - Emit 3DSTATE_HIER_DEPTH_BUFFER on pre-BDW systems - Only use HiZ for single-subpass renderpasses - Emit the HiZ instruction before the stencil instruction to follow the optimized clear sequence specified in the PRMs - Don't modify clear params - Enable resolves when a HiZ buffer is used to ensure depth buffer validity Provides an FPS increase of ~15% on the Sascha triangle and multisampling demos. Signed-off-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: Chad Versace <chadversary@chromium.org> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* anv/cmd_buffer: Add code for performing HZ operationsNanley Chery2016-10-071-0/+187
| | | | | | | | | Create a function that performs one of three HiZ operations - depth/stencil clears, HiZ resolve, and depth resolves. Signed-off-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Chad Versace <chadversary@chromium.org>
* anv: Move cmd_buffer_config_l3 into anv_cmd_buffer.cJason Ekstrand2016-09-031-1/+1
| | | | | | | | This is the only remaining part of genX_l3.c and there's really no good reason for it to be in its own file. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* anv: Add proper support for depth clampingJason Ekstrand2016-06-201-3/+4
| | | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Cc: "12.0" <mesa-stable@lists.freedesktop.org>
* anv/cmd_buffer: Split emit_viewport in twoJason Ekstrand2016-06-201-12/+26
| | | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Cc: "12.0" <mesa-stable@lists.freedesktop.org>
* i965: Fix shared local memory size for Gen9+.Kenneth Graunke2016-06-121-9/+1
| | | | | | | | | | | | | | | | | | | | | Skylake changes the representation of shared local memory size: Size | 0 kB | 1 kB | 2 kB | 4 kB | 8 kB | 16 kB | 32 kB | 64 kB | ------------------------------------------------------------------- Gen7-8 | 0 | none | none | 1 | 2 | 4 | 8 | 16 | ------------------------------------------------------------------- Gen9+ | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | The old formula would substantially underallocate the amount of space. This fixes GPU hangs on Skylake when running with full thread counts. v2: Fix the Vulkan driver too, use a helper function, and fix the table in the comments and commit message. Cc: "12.0" <mesa-stable@lists.freedesktop.org> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Francisco Jerez <currojerez@riseup.net> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* anv: Support new local ID generation & cross-thread constantsJordan Justen2016-06-011-8/+5
| | | | | | | | | | | | | | | | | The cross thread constant support appears on Haswell. It allows us to upload a set of uniform data for all threads without duplicating it per thread. We also support per-thread data which allows us to store a per-thread ID in one of the uniforms that can be used to calculate the gl_LocalInvocationIndex and gl_LocalInvocationID variables. v4: * Support the old local ID push constant layout as well (Jason) Cc: "12.0" <mesa-stable@lists.freedesktop.org> Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* i965: Store number of threads in brw_cs_prog_dataJordan Justen2016-06-011-1/+1
| | | | | | Cc: "12.0" <mesa-stable@lists.freedesktop.org> Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* anv/cmd_buffer: Only emit PIPE_CONTROL on-demandJason Ekstrand2016-05-271-0/+2
| | | | | | | | | | | This is in contrast to emitting it directly in vkCmdPipelineBarrier. This has a couple of advantages. First, it means that no matter how many vkCmdPipelineBarrier calls the application strings together it gets one or two PIPE_CONTROLs. Second, it allow us to better track when we need to do stalls because we can flag when a flush has happened and we need a stall. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* anv: Fix warning: unused variable ‘cs_prog_data’Jordan Justen2016-05-171-1/+0
| | | | | | | This was introduced in 8a80af282091e692da7bf4e412918ba2362dfb4f. Reported-by: Jason Ekstrand <jason@jlekstrand.net> Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
* anv: Port L3 cache programming from i965Jordan Justen2016-05-171-73/+1
| | | | | Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Acked-by: Jason Ekstrand <jason@jlekstrand.net>
* anv: fix warnings in release buildGrazvydas Ignotas2016-04-251-1/+1
| | | | | | | | | Mark variables MAYBE_UNUSED to avoid unused-but-set-variable warnings in release build. Signed-off-by: Grazvydas Ignotas <notasas@gmail.com> Reviewed-by: Chad Versace <chad.versace@intel.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
* anv: s/anv_batch_emit_blk/anv_batch_emit/Jason Ekstrand2016-04-201-20/+18
| | | | Acked-by: Kristian Høgsberg <krh@bitplanet.net>
* anv/gen8_cmd_buffer: Use the new emit macroJason Ekstrand2016-04-201-74/+87
| | | | Acked-by: Kristian Høgsberg <krh@bitplanet.net>
* anv: Remove default scissor and viewport conceptsNanley Chery2016-04-131-23/+4
| | | | | | | | | | | | | Users should never provide a scissor or viewport count of 0 because they are required to set such state in a graphics pipeline. This behavior was previously only used in Meta, which actually just disables those hardware operations at pipeline creation time. Kristian noticed that the current assignment of viewport count reduces the number of viewport uploads, so it is not removed. Signed-off-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: Kristian Høgsberg Kristensen <kristian.h.kristensen@intel.com>
* anv: Invalidate state cache before L3 partitioning set-up.Jordan Justen2016-03-281-0/+1
| | | | | | Port 10d84ba9f084174a1e8e7639dfb05dd855ba86e8 to anv. Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
* anv: Fix cache pollution race during L3 partitioning set-up.Jordan Justen2016-03-281-10/+26
| | | | | | Port 0aa4f99f562a05880a779707cbcd46be459863bf to anv. Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
* anv: Use genxml register support for L3 Cache configJordan Justen2016-03-251-17/+16
| | | | | | | The programming of the L3 Cache registers should match the previous manually packed LRI values. Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
* anv/genX: Add flush_pipeline_select_gpgpuJordan Justen2016-03-121-22/+1
| | | | Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
* anv/cmd_buffer: Pull the core of flush_state into genX_cmd_bufferJason Ekstrand2016-03-081-132/+3
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* anv/cmd_buffer: Split flush_state into two functionsJason Ekstrand2016-03-081-1/+10
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* anv: Store prog data in pipeline cache streamKristian Høgsberg Kristensen2016-03-051-2/+3
| | | | | We have to keep it there for the cache to work, so let's not have an extra copy in struct anv_pipeline too.
* anv/hsw: Move query code to genX file for HaswellJordan Justen2016-03-051-240/+0
| | | | | | | | This fixes many CTS cases, but will require an update to the kernel command parser register whitelist. (The CS GPRs and TIMESTAMP registers need to be whitelisted.) Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
* anv/cmd_buffer: Let the pipeline set StencilBufferWriteEnable on gen9Jason Ekstrand2016-03-041-3/+0
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* anv/cmd_buffer: Mask stencil reference valuesJason Ekstrand2016-03-041-4/+4
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* anv/pipeline: Set StencilBufferWriteEnable from the pipelineJason Ekstrand2016-03-041-3/+0
| | | | | The hardware docs say that StencilBufferWriteEnable should only be set if StencilTestEnable is set. It seems reasonable to set them together.
* anv/pipeline: Respect pRasterizationState->depthBiasEnableJason Ekstrand2016-03-041-6/+0
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* gen8/cmd_buffer: Properly return flushed push constant stagesJason Ekstrand2016-03-021-1/+3
| | | | | This is required on SKL so that we can properly re-emit binding table pointers commands.
* anv/cmd_buffer: Look at both sides for stencil enableJason Ekstrand2016-03-011-2/+2
| | | | Now it's all consistent with gen9
* anv/cmd_buffer: Clean up stencil state setup on gen8Jason Ekstrand2016-03-011-16/+11
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* anv/cmd_buffer: Dirty push constants when changing pipelines.Jason Ekstrand2016-02-291-0/+11
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* anv/cmd_buffer: Re-emit push constants packets for all stagesJason Ekstrand2016-02-291-12/+12
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* anv: Switch over to the macros in genxmlJason Ekstrand2016-02-201-15/+17
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* Move the intel vulkan driver to src/intel/vulkanJason Ekstrand2016-02-181-0/+914
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