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* intel/blorp: Pass a brw_stage_prog_data to upload_shaderJason Ekstrand2016-11-091-1/+2
| | | | | | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98012 Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com> Cc: "13.0" <mesa-stable@lists.freedesktop.org> (cherry picked from commit 4306c10a885bdd833328a2a4eeb0079aa4f4bae3)
* intel/blorp: Add a flag to make blorp not re-emit dept/stencil buffersJason Ekstrand2016-10-141-6/+6
| | | | | | | | | | | In Vulkan, we want to be able to use blorp to perform clears inside of a render pass. If blorp stomps the depth/stencil buffers packets then we'll have to re-emit them. This gets tricky when secondary command buffers get involved. Instead, we'll simply guarantee that the depth and stencil buffers we pass to blorp (if any) match those already set in the hardware. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965: Rename intelScreen to screen.Kenneth Graunke2016-09-201-1/+1
| | | | | | | | "intelScreen" is wordy and also doesn't fit our style guidelines. "screen" is shorter, which is nice, because we use it fairly often. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
* i965/blorp: Add a copy_miptrees helperJason Ekstrand2016-09-121-0/+69
| | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Chad Versace <chadversary@chromium.org>
* intel/blorp: Work in terms of logical array layersJason Ekstrand2016-09-121-4/+27
| | | | | | | | | | | | | | | | | | When Ivy Bridge introduced array multisampling, someone made the decision to do lots of stuff throughout the driver in terms of physical array layers rather than logical array layers. In ISL, we use logical array layers most of the time and it really makes no sense to use physical array layers in the blorp API. Every time someone passes physical array layers into blorp for an array multisampled surface, they're always divisible by the number of samples and we divide right away. Eventually, I'd like to rework most of the GL driver internals to use logical array layers but that's going to be a big project and will probably happen as part of the ISL conversion. For now, we'll do the conversion in brw_blorp and let blorp just use the logical layers. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* intel/blorp: Add a swizzle parameter to blorp_clearJason Ekstrand2016-09-121-2/+4
| | | | | | | | While we're here, we also re-arrange the parameters to better match the parameter order of blorp_blit. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* intel/blorp: Take a destination swizzle in blorp_blitJason Ekstrand2016-09-121-0/+1
| | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* intel/blorp: Take an isl_swizzle instead of a SWIZZLEJason Ekstrand2016-09-121-1/+27
| | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Use hw generetad primitive copies for layered clearsTopi Pohjolainen2016-09-121-24/+12
| | | | | Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* i965/blorp: Sanity check all layers before actual clearTopi Pohjolainen2016-09-121-2/+5
| | | | | Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* intel/blorp: Add plumbing for setting color clear layer countTopi Pohjolainen2016-09-121-3/+3
| | | | | Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* i965/rbc: Allocate mcs directlyTopi Pohjolainen2016-09-121-4/+6
| | | | | | | | | | | | | | | | such as we do for compressed msaa. In case of non-compressed simgle sampled buffers the allocation of mcs is deferred until there is actually a clear operation that needs the mcs. In case of render buffer compression the mcs buffer always needed and there is no real reason to defer the allocation. By doing it directly allows to drop quite a bit unnecessary complexity. Patch leaves brw_predraw_set_aux_buffers() a no-op. Subsequent patches will re-use it and it seemed cleaner to leave it instead of removing and re-introducing. Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* i965/rbc: Allow integer formats as advertised in isl_format.cTopi Pohjolainen2016-09-121-2/+1
| | | | | | | | | | | | | | | | | | | | | | | Blorp consults brw_is_color_fast_clear_compatible() to see if any restrictions apply for fast clear in addition to the capablities advertised in isl_format.c::format_info[]. On Gen8+ integer formats are backlisted for plain old fast clear but there is no reason why lossless compression shouldn't be supported. In fact, lossless compression of integer formats is already supported for normal render paths. This patch prepares for dropping the delayed allocating of the mcs buffer for lossless compression. Until now the skip of fast clear also prevented the mcs being allocated and hence the lossless compression being effectively turned off for integer formats. Once the mcs buffer is allocated beforehand, the assertion addressed here would start triggering. v2: Drop the assert instead of relaxing it (Jason) Fix typo while at it. Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* intel/blorp: Add a format parameter to blorp_fast_clearJason Ekstrand2016-08-291-1/+3
| | | | | | | | | This allows us to use the actual render format as opposed to the texture format. I don't know that the hardware actually cares in the case of fast clears, but it certainly seems more correct. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Remove the remaining brw prefixes from the blorp.h APIJason Ekstrand2016-08-291-26/+26
| | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965: Move the hiz_op enum to blorpJason Ekstrand2016-08-291-6/+6
| | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Get rid of brw_contextJason Ekstrand2016-08-291-5/+21
| | | | | | | | | | | This commit switches all of blorp from taking a brw_context to taking a blorp_context and, where useful, a void *batch. In the GL driver, we only have one active batch at a time so the brw_context *is* the batch but in Vulkan, batch will point to the anv_cmd_buffer in which we are building instructions. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Take a blorp_context in compile_nir_shaderJason Ekstrand2016-08-291-0/+2
| | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Add an "exec" function pointer to blorp_contextJason Ekstrand2016-08-291-0/+8
| | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Use blorp_address in brw_blorp_surface instead of bo+offsetJason Ekstrand2016-08-291-13/+26
| | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Add driver mocs settings to the contextJason Ekstrand2016-08-291-0/+26
| | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Expose the shader cache through function pointersJason Ekstrand2016-08-291-0/+26
| | | | | | | | | | | | | | | This sanitizes blorp's access to the i965 driver's shader cache by patching it through the blorp_context. When we start using blorp in Vulkan, we will simply have to implement such a caching interface in the Vulkan driver. Note: In my first attempt at this, I simplified it down to a single upload_shader entrypoint and implemented the caching inside of blorp. This doesn't work, however, because the i965 driver will, on occation, dump its entire cache and start over. When this happens, blorp needs to be able to recompile its shaders and re-upload them. It's easiest to just expose the caching interface. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
* i965/blorp: Add a blorp_context struct and init/finish funcsJason Ekstrand2016-08-291-0/+6
| | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Don't clear an empty regionJason Ekstrand2016-08-191-0/+4
| | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965: Split brw_blorp.c/h into multiple filesJason Ekstrand2016-08-171-390/+549
| | | | | | | | | | | This mega-commit pulls most of the i965-specific bits of blorp into the brw_blorp.c/h files which now contain nothing but i965 wrappers around "core blorp" calls. The "core blorp" api is moved into blorp.h and the internal blorp data structures are moved into blorp_priv.h. The new file blorp.c is created to house "core blorp" internals which are pulled from the old brw_blorp.c Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Factor the guts of blorp_hiz_exec into a helperJason Ekstrand2016-08-171-18/+25
| | | | Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Add a new brw_blorp_surf intermediate structJason Ekstrand2016-08-171-89/+121
| | | | | | | | At the moment, this seems to make all of the interfaces messier rather than clener. However, it does provide a representation of a surface that simultaneously contains everything and is completely unaware of miptrees. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Do gen6 stencil offsets up-frontJason Ekstrand2016-08-171-77/+31
| | | | | | | | This keeps all of the nastyness of gen6 stencil on the i965 side of the API line and lets us delete that nasty hand-rolled ISL-based offset path that we were using for ALL_SLICES_AT_EACH_LOD. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Set up HiZ surfaces up-frontJason Ekstrand2016-08-171-9/+57
| | | | Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i964/blorp: Set up most aux surfaces up-frontJason Ekstrand2016-08-171-23/+24
| | | | | | | | | This commit also adds support for an offset for aux surfaces. In GL, this only gets used for HiZ on SNB at the moment. However, in Vulkan, all aux surfaces are at a non-zero offset and that is likely to happen in GL eventually. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Stop using the miptree in state setup for tex/rt surfacesJason Ekstrand2016-08-171-3/+7
| | | | | | | | | | This commit movies us from a miptree model to a surf+bo+offset model. In the GL driver, miptrees are almost always at the start of the bo so the offset is zero but we don't want to always make that assumption. In the sort term, gen6 stencil and HiZ will be at an offset but, in the long term, any Vulkan surface is liable to be at a non-zero offset. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Remove unused fields from blorp_surface_infoJason Ekstrand2016-08-171-3/+0
| | | | | | | The only reason why we need layer or level is that we need the z-offset for 3-D surfaces. Let's just have the one field for that. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Use the generic surface state path for gen8 texturesJason Ekstrand2016-08-171-1/+3
| | | | | | | Now that the generic blorp path uses base level/layer, there's no need to make gen8 special. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Only do offset hacks for fake W-tiling and IMSJason Ekstrand2016-08-171-61/+15
| | | | | | | | | | | | | Since the dawn of time, blorp has used offsets directly to get at different mip levels and array slices of surfaces. This isn't really necessary since we can just use the base level/layer provided in the surface state. While it may have simplified blorp's original design, we haven't been using the blorp path for surface state on gen8 thanks to render compression and there's really no good need for it most of the time. This commit restricts such surface munging to the cases of fake W-tiling and fake interleaved multisampling. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Add a z_offset field to blorp_surface_infoJason Ekstrand2016-08-171-0/+9
| | | | | | | The layer field is in terms of physical layers which isn't quite what the sampler will want for 2-D MS array textures. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Rework hiz rect alignment calculationsJason Ekstrand2016-08-171-8/+15
| | | | | | | | | | | | At the moment, the minify operation does nothing because params.depth.view.base_level is always zero. However, as soon as we start using actual base miplevels and array slices, we are going to need the minification. Also, we only need to align the surface dimensions in the case where we are operating on miplevel 0. Previously, it didn't matter because it aligned on miplevel 0 and, for all other miplevels, the miptree code guaranteed that the level was already aligned. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Map 1-D render targets with DIM_LAYOUT_GEN4_2D as 2D on gen9Jason Ekstrand2016-08-171-0/+6
| | | | | | | | | The sampling hardware can handle them ok. It just looks at the tiling to determine whether it's the new gen9 1-D layout or the old one. The render hardware isn't so smart. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Use the isl_view from the blorp_surface_infoJason Ekstrand2016-08-171-17/+1
| | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Get rid of brw_blorp_surface_info::width/heightJason Ekstrand2016-08-171-24/+6
| | | | | | Instead, we manually mutate the surface size as needed. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Move surface offset calculations into a helperJason Ekstrand2016-08-171-32/+43
| | | | | | | | The helper does a full transformation on the surface to turn it into a new 2-D single-layer single-level surface representing the original layer and level in memory. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Use ISL to compute image offsetsJason Ekstrand2016-08-171-3/+91
| | | | | | | For the moment, we still call the old miptree function; we just assert that the two are equal. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Add an isl_view to blorp_surface_infoJason Ekstrand2016-08-171-11/+27
| | | | | | | | | Eventually, this will be the actual view that gets passed into isl to create the surface state. For now, we just use it for the format and the swizzle. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Move intratile offset calculations out of surface state setupJason Ekstrand2016-08-171-12/+12
| | | | | | | | | Previously we multiplied full x/y offsets, resolved tile aligned buffer offset and intra tile offset based on that. Now we let ISL to take into account the msaa setting and we only multiply the resolved intra tile offsets. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Get rid of brw_blorp_surface_info::array_layoutJason Ekstrand2016-08-171-1/+0
| | | | Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Use isl_msaa_layout instead of intel_msaa_layoutJason Ekstrand2016-08-171-18/+0
| | | | | | We also remove brw_blorp_surface_info::msaa_layout. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Get rid of brw_blorp_surface_info::num_samplesJason Ekstrand2016-08-171-5/+3
| | | | Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Get rid of brw_blorp_surface_info::map_stencil_as_y_tiledJason Ekstrand2016-08-171-10/+2
| | | | | | | Now that we're carrying around the isl_surf, we can just modify it directly instead of passing an extra bit around. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Remove compute_tile_offsetsJason Ekstrand2016-08-171-29/+5
| | | | | | We have a handy little function is ISL that does exactly the same thing. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Create the isl_surf up-frontJason Ekstrand2016-08-171-11/+14
| | | | Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/miptree: Remove the stencil_as_y_tiled parameter from get_tile_masksJason Ekstrand2016-08-171-2/+4
| | | | | | | It's only used to stomp the tiling to Y and it's only used by blorp so there's no reason why blorp can't do it itself. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
generated by cgit v1.1 at 2024-06-07 09:39:26 +0000