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path: root/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
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* i965: Add src/dst interference for certain instructions with hazards.Kenneth Graunke2015-11-301-0/+13
* i965/fs: Don't use Gen7-style scratch block reads on Gen9+.Francisco Jerez2015-11-261-2/+9
* i965: Clean up #includes in the compiler.Matt Turner2015-11-241-2/+1
* i965: Move MRF macros from brw_inst.h to brw_eu.h.Matt Turner2015-11-241-0/+1
* i965: Replace HW_REG with ARF/FIXED_GRF.Matt Turner2015-11-131-3/+2
* i965: Rename GRF to VGRF.Matt Turner2015-11-131-12/+12
* i965: Use brw_reg's nr field to store register number.Matt Turner2015-11-131-17/+17
* i965: Remove fixed_hw_reg field from backend_reg.Matt Turner2015-11-131-2/+2
* i965/fs: split out calculation of payload live rangesConnor Abbott2015-10-301-22/+29
* nir: remove dependency on glslRob Clark2015-10-161-1/+1
* i965: Define FIRST_SPILL_MRF and FIRST_PULL_LOAD_MRF only once and in one placeIago Toral Quiroga2015-10-081-2/+0
* i965/fs: Use MRF registers 21-23 for spilling in gen6Iago Toral Quiroga2015-09-211-4/+7
* i965: Turn BRW_MAX_MRF into a macro that accepts a hardware generationIago Toral Quiroga2015-09-211-8/+8
* i965: Add a debug option for spilling everything in vec4 codeIago Toral Quiroga2015-09-041-1/+1
* util/ra: Make allocating conflict lists optionalJason Ekstrand2015-08-181-1/+1
* i965/reg_allocate: Use make_reg_conflicts_transitiveJason Ekstrand2015-08-181-2/+8
* i965/fs: Don't do redundant RA setup on IVB+Jason Ekstrand2015-08-101-0/+9
* i965/fs: Use dispatch_width instead of reg_width in alloc_reg_setsJason Ekstrand2015-08-101-8/+8
* i965/fs: Don't rely on the default builder to create a null register in emit_...Francisco Jerez2015-07-291-1/+1
* i965/fs: don't make unused payload registers interfereConnor Abbott2015-07-171-1/+6
* i965/fs: remove special case in setup_payload_interference()Connor Abbott2015-07-171-20/+0
* i965/fs: Mark last used ip for all regs read in the payloadJordan Justen2015-07-171-1/+4
* i965/fs: Remove the width field from fs_regJason Ekstrand2015-06-301-3/+1
* i965: Remove the brw_context from the visitorsJason Ekstrand2015-06-231-1/+0
* fs/reg_allocate: Remove the MRF hack helpers from fs_visitorJason Ekstrand2015-06-091-12/+13
* i965/fs: Don't let the EOT send message interfere with the MRF hackJason Ekstrand2015-06-091-2/+15
* i965/fs: Migrate register spills and fills to the IR builder.Francisco Jerez2015-06-091-14/+15
* i965/cs: Mark g0 as used by CS_OPCODE_CS_TERMINATEJordan Justen2015-05-021-0/+4
* i965: Add an INTEL_DEBUG=spill option to test spillingJason Ekstrand2015-04-231-1/+1
* i965: Add a brw_compiler structure and store the register sets in itJason Ekstrand2015-04-221-27/+27
* i965: Add a devinfo field to backend_visitor and use it for gen checksJason Ekstrand2015-04-221-5/+5
* i965/fs: Calculate delta_x and delta_y together.Matt Turner2015-04-211-4/+4
* i965/fs: Ensure delta_x/y are even-aligned registers on Gen6.Matt Turner2015-04-211-2/+2
* i965: Remove useless reg_offset >= 0 tests.Matt Turner2015-04-111-1/+0
* i965/fs: Remove dependency of fs_inst on the visitor class.Francisco Jerez2015-02-101-1/+1
* i965: Factor out virtual GRF allocation to a separate object.Francisco Jerez2015-02-101-25/+25
* i965/fs: Use inst->eot rather than opcodes in register allocation.Kenneth Graunke2015-02-051-11/+10
* i965/fs: Delete is_last_send(); just check inst->eot.Kenneth Graunke2015-02-051-14/+1
* i965: Add SIMD8 URB write low-level IR instructionKristian Høgsberg2014-12-101-1/+15
* i965/fs: Clean up some whitespace in reg_allocate.Matt Turner2014-12-011-2/+2
* i965/fs: Don't set dependency hints on instructions with spilled destinationsJason Ekstrand2014-10-271-0/+8
* i965/fs: Make scratch write instructions use the correct execution sizeJason Ekstrand2014-10-271-1/+1
* i965/fs: Use correct spill offsetsJason Ekstrand2014-10-271-6/+5
* i965/fs: Don't [un]spill multiple registers at a time in SIMD8 modeJason Ekstrand2014-10-271-2/+4
* i965/fs: Compute q-values for register allocation manuallyJason Ekstrand2014-10-241-2/+56
* i965/fs: Don't interfere with too many base registersJason Ekstrand2014-10-241-2/+2
* i965/fs: Properly precolor payload registers on GEN5 in SIMD16Jason Ekstrand2014-10-241-1/+10
* i965/fs: Add another use of MAX_VGRF_SIZEJason Ekstrand2014-10-241-1/+1
* i965/fs: Use the correct regs_written on unspill instructionsJason Ekstrand2014-10-141-0/+1
* i965/fs: Use the correct base_mrf for spilling pairs in SIMD8Jason Ekstrand2014-10-021-3/+4
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