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* i965: solve cubemap negative x/y/z faces buffer offset issue in dEQP.Xu,Randy2016-10-111-1/+3
| | | | | | | | | | | | | | Add the miptree level/slice x/y_offset when count the surface offset in brw_emit_surface_state. The surface offset has two parts, one is from mt->offset, which should be 32 aligned in width/height for tiled buffer; another is from mt->level[current_level].slice[current_slice]. x/y_offset. This fix will solve 12 deqp failure dEQP-EGL.functional.image.create.gles2_cubemap_negative_*_texture Signed-off-by: Xu,Randy <randy.xu@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* i965: get outputs read from nir infoTimothy Arceri2016-10-061-1/+1
| | | | | | | | | | This is a step towards dropping the GLSL IR version of do_set_program_inouts() in i965 and moving towards native nir support. This is important because we want to eventually convert to nir and use its optimisations passes before we can call this GLSL IR pass. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: get uses texture gather from nir infoTimothy Arceri2016-10-061-6/+7
| | | | | | | | | | This is a step towards dropping the GLSL IR version of do_set_program_inouts() in i965 and moving towards native nir support. This is important because we want to eventually convert to nir and use its optimisations passes before we can call this GLSL IR pass. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Eliminate brw->cs.prog_data pointer.Kenneth Graunke2016-10-051-4/+5
| | | | | | | | | | | | Just say no to: - brw->cs.base.prog_data = &brw->cs.prog_data->base.base; We'll just use the brw_stage_prog_data pointer in brw_stage_state and downcast it to brw_cs_prog_data as needed. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Timothy Arceri <timothy.arcero@collabora.com>
* i965: Eliminate brw->wm.prog_data pointer.Kenneth Graunke2016-10-051-7/+14
| | | | | | | | | | | | Just say no to: - brw->wm.base.prog_data = &brw->wm.prog_data->base.base; We'll just use the brw_stage_prog_data pointer in brw_stage_state and downcast it to brw_wm_prog_data as needed. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Timothy Arceri <timothy.arcero@collabora.com>
* i965: Add missing BRW_CS_PROG_DATA to CS work group surface atom.Kenneth Graunke2016-10-041-2/+5
| | | | | | Cc: mesa-stable@lists.freedesktop.org Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* i965: Add missing BRW_NEW_FS_PROG_DATA to render target reads.Kenneth Graunke2016-10-041-1/+3
| | | | | | Cc: mesa-stable@lists.freedesktop.org Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* intel/i965: make gen_device_info mutableLionel Landwerlin2016-09-231-5/+5
| | | | | | | | | | | | Make gen_device_info a mutable structure so we can update the fields that can be refined by querying the kernel (like subslices and EU numbers). This patch does not make any functional change, it just makes gen_get_device_info() fill a structure rather than returning a const pointer. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Rename intelScreen to screen.Kenneth Graunke2016-09-201-4/+4
| | | | | | | | "intelScreen" is wordy and also doesn't fit our style guidelines. "screen" is shorter, which is nice, because we use it fairly often. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
* intel/isl: Add an isl_swizzle structure and use it for isl_view swizzlesJason Ekstrand2016-09-121-23/+8
| | | | | | | | | This should be more compact than the enum isl_channel_select[4] that we were using before. It's also very convenient because we already had such a structure in the Vulkan driver we just needed to pull it over. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965: Add sanity check for non-compressible texture viewsTopi Pohjolainen2016-09-121-0/+34
| | | | | | | v2: Fix missing inline declaration Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* i965/rbc: Consult rb settings for texture surface setupTopi Pohjolainen2016-09-121-7/+60
| | | | | | | | | | | | | | | | | | | | | | | | Once mcs buffer gets allocated without delay for lossless compression (same as we do for msaa), one gets regression in: GL45-CTS.texture_barrier_ARB.same-texel-rw Setting the auxiliary surface for both sampling engine and data port seems to fix this. I haven't found any hardware documentation backing this though. v2 (Jason): Prepare also for the case where surface is sampled with non-compressible format forcing also rendering without compression. v3: Split asserts and decision making. v4: Detailed comment provided by Jason explaining the need for using auxiliary buffer for texturing when the same surface is also used as render target. Added check for existence of renderbuffer before considering if underlying miptree matches. Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* i965: Track non-compressible sampling of renderbuffersTopi Pohjolainen2016-09-121-2/+10
| | | | | | | | | | | | | | | | | v3: - Actually set the flags when needed instead of falsely overwriting them (Jason). - Use more generic name for flag (dropped RENDERBUFFER) - Consult also shader images v4: - Consult only lossless compressd shader images v5: - Check the existence of renderbuffer before considering if it matches the given miptree Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* i965: Replace boolean rb surface state setup argument with flagsTopi Pohjolainen2016-09-121-10/+18
| | | | | | | | | | | And add plumbing to provide it all the way to surface state emitter. This is not used yet but will be in subsequent patches to carry additional constraints. v2 (Jason): Use uint32_t instead of int as the type Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* intel: s/brw_device_info/gen_device_info/Jason Ekstrand2016-09-031-1/+1
| | | | | | | | | | | | | Generated by: sed -i -e 's/brw_device_info/gen_device_info/g' src/intel/**/*.c sed -i -e 's/brw_device_info/gen_device_info/g' src/intel/**/*.h sed -i -e 's/brw_device_info/gen_device_info/g' **/i965/*.c sed -i -e 's/brw_device_info/gen_device_info/g' **/i965/*.cpp sed -i -e 's/brw_device_info/gen_device_info/g' **/i965/*.h Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* i965/gen7: Use R8_UINT stencil copy when sampling the stencil textureJordan Justen2016-08-261-2/+10
| | | | | | | | v2: * Check gen <= 7, rather than gen == 7. (Ian) Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
* i965: Disable hardware blending if advanced blending is in use.Kenneth Graunke2016-08-251-2/+2
| | | | | | | | We'll do blending in the shader in this case, so just disable the hardware blending. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Francisco Jerez <currojerez@riseup.net>
* i965: Upload surface state for non-coherent framebuffer fetch.Francisco Jerez2016-08-251-0/+89
| | | | | | | | This iterates over the list of attached render buffers and binds appropriate surface state structures to the binding table block allocated for shader framebuffer read. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Implement support for overriding the texture target in ↵Francisco Jerez2016-08-251-4/+50
| | | | | | | | | | | | | | | | | | | | | brw_emit_surface_state. This allows the caller to bind a miptree using a texture target other than the one it it was created with. The code should work even if the memory layouts of the specified and original targets don't match, as long as the caller only intends to access a single slice of the miptree structure. This will be exploited by the next commit in order to support non-coherent framebuffer fetch of a single layer of a 3D texture (since some generations lack the minimum array element control for 3D textures bound to the sampler unit), and multiple layers of a 1D array texture (since binding it as an actual 1D array texture would require state-dependent recompiles because the same shader couldn't simultaneously work for 1D and 2D array textures due to the different texel fetch coordinate ordering). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Massage argument list of brw_emit_surface_state().Francisco Jerez2016-08-251-11/+11
| | | | | | | | | | | | | | | | | | This commit does three different things in a single pass in order to keep the amount of churn low: Remove the for_gather boolean argument which was unused, pass the isl_view argument by value rather than by reference since I'll have to modify it from within the function, and add a target argument to allow callers to bind textures using a target other than the original. The prototype of the function now looks like: void brw_emit_surface_state(struct brw_context *brw, struct intel_mipmap_tree *mt, GLenum target, struct isl_view view, uint32_t mocs, uint32_t *surf_offset, int surf_index, unsigned read_domains, unsigned write_domains); Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: report bound buffer size not underlying buffer size for image size (v2)Dave Airlie2016-08-231-2/+2
| | | | | | | | | | | | | | This seems to make sense, the image is bound to a subset of the buffer so the image size should be from the bound size not the underlying object. This fixes: GL44-CTS.shader_image_size.advanced-nonMS-fs-int v2: get mininum of the two values, same as we write to the hw. Reviewed-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Dave Airlie <airlied@redhat.com>
* i965: use new subroutine index uploader.Dave Airlie2016-08-231-0/+2
| | | | | | | | This plugs the subroutine index updates into the i965 backend, where it loads constants. Signed-off-by: Dave Airlie <airlied@redhat.com> Acked-by: Andres Gomez <agomez@igalia.com>
* i965/blorp: Use the generic surface state path for gen8 texturesJason Ekstrand2016-08-171-1/+1
| | | | | | | Now that the generic blorp path uses base level/layer, there's no need to make gen8 special. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* util: Move _mesa_fsl/util_last_bit into util/bitscan.hMathias Fröhlich2016-08-091-1/+1
| | | | | | | | | | | As requested with the initial creation of util/bitscan.h now move other bitscan related functions into util. v2: Split into two patches. Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de> Tested-by: Brian Paul <brianp@vmware.com> Reviewed-by: Brian Paul <brianp@vmware.com>
* i965: Stop muging cube array lengths by 6Jason Ekstrand2016-07-201-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | From the Sky Lake PRM: "For SURFTYPE_CUBE: For Sampling Engine Surfaces and Typed Data Port Surfaces, the range of this field is [0,340], indicating the number of cube array elements (equal to the number of underlying 2D array elements divided by 6). For other surfaces, this field must be zero." In other words, the depth field for cube maps is in number of cubes not number of 2-D slices so we need to divide by 6. ISL will do this correctly for us assuming that we provide it with the correct array bounds which it expects to be in 2-D slices. It appears as if we've been doing this wrong ever since we first added cube map arrays for Sandy Bridge and the change to ISL made things slightly worse. While we're at it, we now need to remoe the shader hacks we've always done since they were only needed because we were setting the depth field six times too large. v2: Fix the vec4 backend as well (not sure how I missed this). Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Reviewed-by: Chris Forbes <chrisforbes@google.com>
* i965: Use tex_mocs instead of rb_mocs for GL images.Kenneth Graunke2016-07-191-1/+1
| | | | | | | | | | | | | | Fixes a 10-20% performance regression in OglCSDof caused by commit 5a8c89038abab0184ea72664ab390ec6ca58b4d6, which made images (in the image load/store sense) use BDW_MOCS_PTE instead of BDW_MOCS_WB. This seems sketchy, as the default PTE value is supposed to be WB LLC eLLC, which is the same as our MOCS WB setting. It's only supposed to change when using a surface for display, which won't ever happen for images. Something may be wrong in the kernel... Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* i965: Skip update_texture_surface when the plane doesn't existJason Ekstrand2016-07-181-8/+10
| | | | | | | | | Thanks to rebase fail, recent surface state changes (commits 7e951cd56, 8521ce1a7, and 69c0dc5c53) effectively reverted 727a9b24933 and 367cf3a2e3e which was unintentional. This should bring it back. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* i965/context: Remove some unnecessary vfuncsJason Ekstrand2016-07-151-2/+1
| | | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Chad Versace <chad.versace@intel.com>
* i965: Get rid of gen6_surface_state.cJason Ekstrand2016-07-151-0/+7
| | | | | | | | | The only useful thing left was gen6_init_vtable_surface_functions which we can easily put in brw_wm_surface_state.c. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Chad Versace <chad.versace@intel.com>
* i965: Use ISL for emitting buffer surface statesJason Ekstrand2016-07-151-49/+44
| | | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Chad Versace <chad.versace@intel.com>
* i965/state: Account for the element size in emit_buffer_surface_stateJason Ekstrand2016-07-151-5/+6
| | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/gen4-6: Use the generic ISL-based path for texture surfacesJason Ekstrand2016-07-151-93/+1
| | | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Chad Versace <chad.versace@intel.com>
* i965/state: Add generic surface update functions based on ISLJason Ekstrand2016-07-151-0/+185
| | | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Chad Versace <chad.versace@intel.com>
* i965/surface_state: Rename brw_update to gen4_updateJason Ekstrand2016-07-151-11/+11
| | | | | | | | | We're about to add generic versions which work across gens and those should have the brw name. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Chad Versace <chad.versace@intel.com>
* i965/state: Use ISL for emitting image surfacesJason Ekstrand2016-07-151-11/+22
| | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Chad Versace <chad.versace@intel.com>
* i965/state: Add a helper for emitting a surface state using islJason Ekstrand2016-07-151-0/+81
| | | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Chad Versace <chad.versace@intel.com>
* glsl/mesa: split gl_shader in twoTimothy Arceri2016-06-301-3/+3
| | | | | | | | | | | | | | | | | There are two distinctly different uses of this struct. The first is to store GL shader objects. The second is to store information about a shader stage thats been linked. The two uses actually share few fields and there is clearly confusion about their use. For example the linked shaders map one to one with a program so can simply be destroyed along with the program. However previously we were calling reference counting on the linked shaders. We were also creating linked shaders with a name even though it is always 0 and called the driver version of the _mesa_new_shader() function unnecessarily for GL shader objects. Acked-by: Iago Toral Quiroga <itoral@igalia.com>
* i965: Use miptree to decide format on multi-plane images for gen < 7Jordan Justen2016-06-261-1/+2
| | | | | | | | | | | This wasn't handled correctly for multi-plane images on gen < 7 in 727a9b24933d384f5440ed4318fb720ed11d6dd1. Reported-by: Mark Janes <mark.a.janes@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96674 Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Cc: "12.0" <mesa-stable@lists.freedesktop.org> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* i965: Skip update_texture_surface when the plane doesn't existJordan Justen2016-06-241-9/+6
| | | | | | | | | Reported-by: Grazvydas Ignotas <notasas@gmail.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96607 Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Cc: Kristian Høgsberg <krh@bitplanet.net> Cc: "12.0" <mesa-stable@lists.freedesktop.org> Reviewed-by: Chad Versace <chad.versace@intel.com>
* i965/gen4: Subtract 1 from buffer sizesJason Ekstrand2016-06-221-3/+3
| | | | | | | | | The PRM states that the values put in Width, Height, and Depth should be various bits from the value size - 1. We seem to have done this wrong more-or-less from the start. Reviewed-by: Chad Versace <chad.versace@intel.com> Cc: "11.1 11.2 12.0" <mesa-stable@lists.freedesktop.org>
* i965: Remove fake W-tiled render target supportJason Ekstrand2016-06-221-25/+0
| | | | | | | This hasn't been used since 1cfb4bc890b8 where we deleted the meta stencil blit path. Reviewed-by: Chad Versace <chad.versace@intel.com>
* i965/gen4-6: Handle gl_texture_object::BaseLevel and MinLayer correctlyJason Ekstrand2016-06-221-1/+3
| | | | | | | | | This is basically a direct translation of what we do for gen7. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83036 Cc: "11.1 11.2 12.0" <mesa-stable@lists.freedesktop.org>
* i965/gen4: Pull texture formats from the texture object not the miptreeJason Ekstrand2016-06-221-1/+1
| | | | | | | | | | | This makes texture views sort-of work. It doesn't add full texture view support for gen4-5 but it is enough to fix the GL_ARB_copy_image formats piglit test on Iron Lake. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83036 Cc: "11.1 11.2 12.0" <mesa-stable@lists.freedesktop.org>
* i965: Emit surface states for extra planes prior to gen8Jason Ekstrand2016-06-081-0/+9
| | | | | | | | | | When Kristian implemented GL_TEXTURE_EXTERNAL_OES, he hooked it up for gen8 but not for gen7 or earlier. It all works, we just need to emit the states for the extra planes. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kristian Høgsberg <krh@bitplanet.net> Cc: "12.0" <mesa-stable@lists.freedesktop.org>
* i965: Support textures with multiple planesKristian Høgsberg Kristensen2016-05-241-16/+22
| | | | Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* i965: Make all atoms to track BRW_NEW_BLORP by defaultKenneth Graunke2016-04-231-2/+14
| | | | Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com
* i965/surface_state: Use libisl functions for image format loweringJason Ekstrand2016-04-211-9/+12
| | | | | | | This lets us delete some redundant code and keep all of the image_load_store format lowering logic in one place: libisl. Reviewed-by: Chad Versace <chad.versace@intel.com>
* i965: Allow texture surface state setup to be used by blorpTopi Pohjolainen2016-04-211-1/+2
| | | | | Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Reupload push and pull constants when we get new shader image unit state.Francisco Jerez2016-02-131-0/+5
| | | | | | | | | | | Fixes several of the "dEQP-GLES31.functional.image_load_store*load_store*single_layer" dEQP tests that use image formats we implement using untyped surface messages. Cc: mesa-stable@lists.freedesktop.org Tested-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Split brw_upload_texture_surfaces into compute/render atoms.Kenneth Graunke2016-02-111-7/+31
| | | | | | | | | | | When uploading state for the compute pipeline, we don't want to look at VS/TCS/TES/GS/FS programs, as they might be stale, and aren't relevant anyway. Likewise, the render pipeline shouldn't look at CS. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93790 Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
generated by cgit v1.1 at 2024-05-29 01:54:43 +0000