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src
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mesa
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drivers
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dri
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i965
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gen6_depth_state.c
Commit message (
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Author
Age
Files
Lines
*
i965/gen6: Set up layer constraints properly for depth buffers.
Kenneth Graunke
2015-07-10
1
-1
/
+5
*
i965: Rename intel_emit* to reflect their new location in brw_pipe_control
Chris Wilson
2015-06-24
1
-1
/
+1
*
i965/hiz: Start to separate miptree out from hiz buffers
Jordan Justen
2015-03-09
1
-1
/
+1
*
i965: Do Sandybridge workaround flushes before each primitive.
Kenneth Graunke
2015-02-17
1
-7
/
+0
*
i965/gen6: Stencil/hiz needs an offset for LOD > 0
Jordan Justen
2014-08-15
1
-2
/
+32
*
i965/gen6 depth surface: program 3DSTATE_DEPTH_BUFFER to top of surface
Jordan Justen
2014-08-15
1
-8
/
+27
*
i965/gen6 depth surface: calculate minimum array element being rendered
Jordan Justen
2014-08-15
1
-0
/
+2
*
i965/gen6 depth surface: calculate LOD being rendered to
Jordan Justen
2014-08-15
1
-0
/
+3
*
i965/gen6 depth surface: calculate depth (array size) for depth surface
Jordan Justen
2014-08-15
1
-0
/
+3
*
i965/gen6 depth surface: calculate more specific surface type
Jordan Justen
2014-08-15
1
-0
/
+33
*
i965/gen6_depth_state.c: Remove (gen != 6) code paths
Jordan Justen
2014-08-15
1
-31
/
+14
*
i965: Split gen6 depth hiz state out from brw
Jordan Justen
2014-08-15
1
-0
/
+176