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* i965/mt: Disable aux surfaces after making miptree shareableChad Versace2016-12-141-0/+2
| | | | | | | | | | | | | | | The entire goal of intel_miptree_make_shareable() is to permanently disable the miptree's aux surfaces. So set intel_mipmap_tree:disable_aux_buffers after the function's done with discarding down the aux surfaces. References: https://bugs.freedesktop.org/show_bug.cgi?id=98329 Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Cc: Nanley Chery <nanley.g.chery@intel.com Cc: Haixia Shi <hshi@chromium.org> Cc: mesa-stable@lists.freedesktop.org (cherry picked from commit 1c8be049bea786c2c054a770025976beba5b8636)
* intel/i965: make gen_device_info mutableLionel Landwerlin2016-09-231-2/+2
| | | | | | | | | | | | Make gen_device_info a mutable structure so we can update the fields that can be refined by querying the kernel (like subslices and EU numbers). This patch does not make any functional change, it just makes gen_get_device_info() fill a structure rather than returning a const pointer. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Rename intelScreen to screen.Kenneth Graunke2016-09-201-2/+2
| | | | | | | | "intelScreen" is wordy and also doesn't fit our style guidelines. "screen" is shorter, which is nice, because we use it fairly often. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
* i965/rbc: Allocate mcs directlyTopi Pohjolainen2016-09-121-52/+16
| | | | | | | | | | | | | | | | such as we do for compressed msaa. In case of non-compressed simgle sampled buffers the allocation of mcs is deferred until there is actually a clear operation that needs the mcs. In case of render buffer compression the mcs buffer always needed and there is no real reason to defer the allocation. By doing it directly allows to drop quite a bit unnecessary complexity. Patch leaves brw_predraw_set_aux_buffers() a no-op. Subsequent patches will re-use it and it seemed cleaner to leave it instead of removing and re-introducing. Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* intel: Rename brw_get_device_name/info to gen_get_device_name/infoJason Ekstrand2016-09-031-1/+1
| | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* i965: Move the hiz_op enum to blorpJason Ekstrand2016-08-291-9/+9
| | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965: Add function to copy a stencil miptree to an R8_UINT miptreeJordan Justen2016-08-261-1/+56
| | | | | | | | | v2: * Cleanups suggested by Ian, Matt and Topi Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/gen7: Add R8_UINT stencil miptree copy for samplingJordan Justen2016-08-261-0/+2
| | | | | | | | | | | For gen < 8, we can't sample from the stencil buffer, which is required for the ARB_stencil_texturing extension. We'll make a copy of the stencil data into a new texture that we can sample using the R8_UINT surface type. Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965: Fix assert with multisampling and cubemapsJordan Justen2016-08-261-2/+4
| | | | | Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
* i965: Return the correct layout from get_isl_dim_layout for pre-ILK cube ↵Francisco Jerez2016-08-251-2/+5
| | | | | | textures. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Factor out isl_surf_dim/isl_dim_layout calculation into functions.Francisco Jerez2016-08-251-23/+48
| | | | | | | | The logic to calculate the right layout and dimensionality for a given GL texture target is going to be useful elsewhere, factor it out from intel_miptree_get_isl_surf(). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Return whether the miptree was resolved from ↵Francisco Jerez2016-08-251-4/+8
| | | | | | | | | intel_miptree_resolve_color(). This will allow optimizing out the cache flush in some cases when resolving wasn't necessary. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/miptree: Add real support for HiZJason Ekstrand2016-08-171-13/+28
| | | | | | | | The previous HiZ support was bogus because all of get_aux_isl_surf looked at mt->mcs_mt directly. For HiZ buffers, you need to look at either mt->hiz_buf or mt->hiz_buf->mt. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/miptree: Use the isl helpers for creating aux surfacesJason Ekstrand2016-08-171-46/+9
| | | | | | | | | | | In order for the calculations of things such as fast clear rectangles to work, we need more details of the auxiliary surface to be correct. In particular, we need to be able to trust the width and height fields. (These are not necessarily what you want coming out of the miptree.) The only values state setup really cares about are the row and array pitch and those we can safely stomp from the miptree. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/miptree: Use mcs_mt->qpitch for aux surfacesJason Ekstrand2016-08-171-1/+2
| | | | | | | At one point, we were doing this correctly. It must have gotten lost in one of the many rebases. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/miptree: Allow get_aux_isl_surf when there is no aux surfaceJason Ekstrand2016-08-171-1/+2
| | | | Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/miptree: Support depth in get_isl_clear_colorJason Ekstrand2016-08-171-1/+6
| | | | Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/miptree: Fill out the isl_surf::usage fieldJason Ekstrand2016-08-171-1/+24
| | | | Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/miptree: Remove the stencil_as_y_tiled parameter from get_tile_masksJason Ekstrand2016-08-171-4/+1
| | | | | | | It's only used to stomp the tiling to Y and it's only used by blorp so there's no reason why blorp can't do it itself. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965: use mt->offset in intel_miptree_map_movntdqa()Haixia Shi2016-08-031-0/+3
| | | | | | | | | | | We need to include mt->offset in the calculation of src pointer because its value may be non-zero, for example in a cubemap texture. Signed-off-by: Haixia Shi <hshi@chromium.org> Cc: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Chad Versace <chad@kiwitree.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Change-Id: I461ad5b204626d5a1c45611fc6b63735dcf29f63
* i965/miptree: Stop multiplying cube depth by 6 in HiZ calculationsJason Ekstrand2016-07-261-17/+2
| | | | | | | | | intel_mipmap_tree::logical_depth0 is now in number of 2D slices so we no longer need to be multiplying by 6. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com> Cc: "12.0" <mesa-stable@lists.freedesktop.org>
* i965/miptree/isl: Stop multiplying depth by 6 for cubesJason Ekstrand2016-07-261-5/+0
| | | | | | | | | | Now that the logical_depth0 field is in number of 2D slices, we don't need to be multiplying by 6 when creating the surface. It wasn't hurting anything primarily because we get the actual length from the view which was already handling it correctly. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
* i965/miptree: Set logical_depth0 == 6 for cube mapsJason Ekstrand2016-07-201-4/+11
| | | | | | | | | | | | | This matches what we do for cube maps where logical_depth0 is in number of face-layers rather than number of cubes. This does mean that we will temporarily be setting the surface bounds too loose for cube map textures but we are already setting them too loose for cube arrays and we will be fixing that in the next commit anyway. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Reviewed-by: Chris Forbes <chrisforbes@google.com> Cc: "12.0 11.2 11.1" <mesa-stable@lists.freedesktop.org>
* i965/miptree: Enforce that height == 1 for 1-D array texturesJason Ekstrand2016-07-201-19/+3
| | | | | | | | | | | | | | | | | | | The GL API and mesa internals do this differently than we do. In GL, there is no depth parameter for 1-D arrays and height is used. In the i965 miptree code we do the sane thing and make height == 1 and use depth for number of slices. This makes for a mismatch every time we create a 1-D array texture from GL. Instead of actually solving this problem, we just said "1-D is hard, let's make sure it works no matter which way we pass the parameters" and called it a day. This commit fixes the one GL -> i965 transition point where we weren't already handling 1-D array textures to do the right thing and then replaces the magic fixup code with an assert that you're doing the right thing. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Reviewed-by: Chris Forbes <chrisforbes@google.com> Cc: "12.0 11.2 11.1" <mesa-stable@lists.freedesktop.org>
* i965/miptree: Add a helper for getting the aux isl_surf from a miptreeJason Ekstrand2016-07-151-0/+117
| | | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Chad Versace <chad.versace@intel.com>
* i965/miptree: Add a helper for getting the ISL clear color from a miptreeJason Ekstrand2016-07-151-0/+26
| | | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Chad Versace <chad.versace@intel.com>
* i965/miptree: Add a helper for getting an isl_surf from a miptreeJason Ekstrand2016-07-151-2/+170
| | | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Chad Versace <chad.versace@intel.com>
* i965: Add norbc debug optionTopi Pohjolainen2016-06-011-0/+2
| | | | | | | | | | | | | | This INTEL_DEBUG option disables lossless compression (also known as render buffer compression). v2: (Matt) Use likely(!lossless_compression_disabled) instead of !likely(lossless_compression_disabled) (Grazvydas) Update docs/envvars.html Cc: "12.0" <mesa-stable@lists.freedesktop.org> Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Create multiple miptrees for planar YUV imagesKristian Høgsberg Kristensen2016-05-241-0/+3
| | | | Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* i965: Use ISL for surface format introspectionJason Ekstrand2016-05-231-1/+4
| | | | | With this, we can delete the surface format table in brw_surface_formats.c because all of the information we need is now in ISL.
* i965: Mark is_lossless_compressed_aux UNUSED to silence warning.Matt Turner2016-05-161-1/+1
| | | | Used only in assert().
* i965: Use blorp for all updownsample blitsJason Ekstrand2016-05-141-24/+10
| | | | | | | We used to use a meta path because blorp didn't support 16x MSAA. Now it does, so we don't need the meta paths anymore. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/gen9: Enable lossless compressionTopi Pohjolainen2016-05-121-3/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I tried first creating the auxiliary buffer the same time with the color buffer. That, however, led me into a situation where we would later create the rest of the mip-levels and the compression would need to be disabled (it is only supported for single level buffers). Here we try to create it on demand just before the hardware starts to render. This is similar what we do with fast clear buffers, their creation is deferred until the first clear. This setup also gives the opportunity to detect if the miptree represents the temporaty texture used internally in the mesa core. This texture is mostly written by cpu and therefore enabling compression for it doesn't make much sense. Note that a heuristic is included. Floating point formats are not enabled yet as they are only seen to hurt performance. Some highlights with window system driver kept fixed to default and only the application driver changing: Manhattan: 8.32152% +/- 0.355881% Offscreen: 9.09713% +/- 0.340763% Glb trex: 8.46231% +/- 0.460624% Offscreen: 9.31872% +/- 0.463743% v2 (Ben): Re-use msaa layout type for single sampled case. v3: Moved the deferred allocation of mcs to brw_try_draw_prims() and brw_blorp_blit_miptrees() instead. v4: (Ken): Drop MIPTREE_LAYOUT_ACCELERATED_UPLOAD when allocating mcs. Do not enable for scanout buffers Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
* i965: Deferred allocation of mcs for lossless compressedTopi Pohjolainen2016-05-121-0/+40
| | | | | | | | | | | | | | | | | | | | Until now mcs was associated to single sampled buffers only for fast clear purposes and it was therefore the responsibility of the clear logic to allocate the aux buffer when needed. Now that normal 3D render or blorp blit may render with mcs enabled also, they need to prepare the mcs just as well. v2: Do not enable for scanout buffers v3 (Ben): - Fix typo in commit message. - Check for gen < 9 and return early in brw_predraw_set_aux_buffers() - Check for gen < 9 and return early in intel_miptree_prepare_mcs() v4: Check for msaa_layput and number of samples to determine if lossless compression is to used. Otherwise one cannot distuingish between fast clear with and without compression. Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
* i965: Add flag telling if miptree is for client consumptionTopi Pohjolainen2016-05-121-3/+4
| | | | | | | | | | | | | | Consider later on adding specific disable flags such as MIPTREE_LAYOUT_DISABLE_AUX_MCS = 1 << 3, /* CCS_D */ MIPTREE_LAYOUT_DISABLE_AUX_CCS_E = 1 << 4, MIPTREE_LAYOUT_DISABLE_AUX = MIPTREE_LAYOUT_DISABLE_AUX_MCS | MIPTREE_LAYOUT_DISABLE_AUX_CCS_E, and equivalent boolean/enums into miptree. Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
* i965: Add helper for lossless compression supportTopi Pohjolainen2016-05-121-0/+26
| | | | | | | | | | | v2: Check explicitly against base type of GL_FLOAT instead of using _mesa_is_format_integer_color(). Otherwise we miss GL_UNSIGNED_NORMALIZED. v3 (Ben): Also call intel_miptree_supports_non_msrt_fast_clear() in order to really check everything. Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
* i965: Relax assertion of halign == 16 for lossless compressed auxTopi Pohjolainen2016-05-121-1/+6
| | | | | Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
* Revert "i965: Always use Y-tiled buffers on SKL+"Daniel Stone2016-05-091-8/+2
| | | | | | | | | | | | | | | | | | | This commit broke Weston, Mutter, and xf86-video-modesetting, on KMS. In order to use Y-tiled buffers, the kernel requires the tiling mode to be explicitly named through the I915_FORMAT_MOD_Y_TILED AddFB2 modifier; it disallows any attempt to infer the buffer's tiling mode. As the GBM API does not have a way to extract modifiers for a buffer, this commit broke all users of GBM on SKL+. Revert it for now, until we get a way to extract modifier information from GBM, and also let GBM users inform the implementation that it intends to use the modifiers. This reverts commit 6a0d036483caf87d43ebe2edd1905873446c9589. Signed-off-by: Daniel Stone <daniels@collabora.com> Acked-by: Ben Widawsky <ben@bwidawsk.net> Tested-by: Hans de Goede <hdegoede@redhat.com>
* i965: Fix MapTextureImage for multi-slice/level stencil buffers.Kenneth Graunke2016-04-261-2/+2
| | | | | | | | | | | We called intel_miptree_get_image_offset() to get the image offsets for the current level/slice, but then proceeded to ignore the results and clobber level/slice 0 every time. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94713 Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
* i965/blorp: Enable for buffer resolvesTopi Pohjolainen2016-04-231-1/+1
| | | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94181 Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/blorp: Add support for 2x msaaTopi Pohjolainen2016-04-221-3/+2
| | | | | Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Always use Y-tiled buffers on SKL+Ben Widawsky2016-04-211-2/+8
| | | | | | | | | | | | | | | | Starting with Skylake, the display engine is capable of scanning out from Y-tiled buffers. As such, we can and should use Y-tiling for better efficiency. This also has the added benefit of being able to fast clear the winsys buffer. Note that the buffer allocation done for mipmaps will already never allocate an X-tiled buffer for GEN9. This has an almost universal positive impact on benchmarks, some improving by as much as 20%. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Declare input to mcs alignment calculation constantTopi Pohjolainen2016-04-211-1/+1
| | | | | Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/blorp: Enable blits on gen8Topi Pohjolainen2016-04-211-2/+1
| | | | | | | | v2 (Ken): Moved switch cases for gen8/9 in texel_fetch() to earlier patch adding gen8/9 sampling support. Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/blorp: Add check for supported sample numbersTopi Pohjolainen2016-04-211-2/+7
| | | | | | | | v2 (Ken): Fix the condition on using meta for stencil blits: use_blorp -> !use_blorp Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/blorp: Add support for source swizzleTopi Pohjolainen2016-04-211-2/+3
| | | | | | | | | | | | | In order to support cases where gen9 uses RGBA format to back client requested RGB, one needs to have means to force alpha channel to one when user requested RGB surface is used as blit source. v2 (Ken): Use helper for constructing the swizzle (this should be changed to use brw_get_texture_swizzle() as a follow-up). Also calculate the swizzle for CopyTexSubImage. Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Define miptree map functions static (trivial)Ben Widawsky2016-04-181-2/+2
| | | | | | | | | | | | | They were already declared as such. It was changed here: commit 31f0967fb50101437d2568e9ab9640ffbcbf7ef9 Author: Ian Romanick <ian.d.romanick@intel.com> Date: Wed Sep 2 14:43:18 2015 -0700 i965: Make intel_miptree_map_raw static Cc: Ian Romanick <ian.d.romanick@intel.com> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com> Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
* i965/blorp: Refactor sRGB encoding/decoding.Kenneth Graunke2016-03-211-2/+4
| | | | | | | | | | | | Because the rules for sRGB are so insane, we change brw_blorp_miptrees to take decode_srgb and encode_srgb flags, which control linearization of the source and destination separately. This should make it easy to implement whatever crazy combination of rules people throw at us. For now, it should be equivalent. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965: Expose logic telling if non-msrt mcs is supportedTopi Pohjolainen2016-02-161-4/+5
| | | | | | | | | Alos use the opportunity to mark inputs constant. (Context has to be given as read-write to intel_miptree_supports_non_msrt_fast_clear() to support debug output). Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
* i965/gen9: Refactor msrt mcs initializationTopi Pohjolainen2016-02-161-14/+22
| | | | | | | | This will be re-used to initialize auxiliary buffers in lossless compression case. Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
generated by cgit v1.1 at 2024-05-16 11:00:16 +0000