summaryrefslogtreecommitdiffstats
path: root/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
Commit message (Collapse)AuthorAgeFilesLines
* i965/rbc: Allocate mcs directlyTopi Pohjolainen2016-09-121-5/+2
| | | | | | | | | | | | | | | | such as we do for compressed msaa. In case of non-compressed simgle sampled buffers the allocation of mcs is deferred until there is actually a clear operation that needs the mcs. In case of render buffer compression the mcs buffer always needed and there is no real reason to defer the allocation. By doing it directly allows to drop quite a bit unnecessary complexity. Patch leaves brw_predraw_set_aux_buffers() a no-op. Subsequent patches will re-use it and it seemed cleaner to leave it instead of removing and re-introducing. Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* intel: Rename brw_get_device_name/info to gen_get_device_name/infoJason Ekstrand2016-09-031-1/+1
| | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* i965: Move the hiz_op enum to blorpJason Ekstrand2016-08-291-1/+1
| | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965: Add function to copy a stencil miptree to an R8_UINT miptreeJordan Justen2016-08-261-0/+4
| | | | | | | | | v2: * Cleanups suggested by Ian, Matt and Topi Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/gen7: Add R8_UINT stencil miptree copy for samplingJordan Justen2016-08-261-0/+12
| | | | | | | | | | | For gen < 8, we can't sample from the stencil buffer, which is required for the ARB_stencil_texturing extension. We'll make a copy of the stencil data into a new texture that we can sample using the R8_UINT surface type. Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965: Factor out isl_surf_dim/isl_dim_layout calculation into functions.Francisco Jerez2016-08-251-0/+7
| | | | | | | | The logic to calculate the right layout and dimensionality for a given GL texture target is going to be useful elsewhere, factor it out from intel_miptree_get_isl_surf(). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Return whether the miptree was resolved from ↵Francisco Jerez2016-08-251-1/+1
| | | | | | | | | intel_miptree_resolve_color(). This will allow optimizing out the cache flush in some cases when resolving wasn't necessary. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/miptree: Remove the stencil_as_y_tiled parameter from get_tile_masksJason Ekstrand2016-08-171-1/+0
| | | | | | | It's only used to stomp the tiling to Y and it's only used by blorp so there's no reason why blorp can't do it itself. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/miptree: Add a helper for getting the aux isl_surf from a miptreeJason Ekstrand2016-07-151-0/+5
| | | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Chad Versace <chad.versace@intel.com>
* i965/miptree: Add a helper for getting the ISL clear color from a miptreeJason Ekstrand2016-07-151-0/+4
| | | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Chad Versace <chad.versace@intel.com>
* i965/miptree: Add a helper for getting an isl_surf from a miptreeJason Ekstrand2016-07-151-0/+6
| | | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Chad Versace <chad.versace@intel.com>
* i965: Create multiple miptrees for planar YUV imagesKristian Høgsberg Kristensen2016-05-241-0/+5
| | | | Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* i965: Deferred allocation of mcs for lossless compressedTopi Pohjolainen2016-05-121-0/+4
| | | | | | | | | | | | | | | | | | | | Until now mcs was associated to single sampled buffers only for fast clear purposes and it was therefore the responsibility of the clear logic to allocate the aux buffer when needed. Now that normal 3D render or blorp blit may render with mcs enabled also, they need to prepare the mcs just as well. v2: Do not enable for scanout buffers v3 (Ben): - Fix typo in commit message. - Check for gen < 9 and return early in brw_predraw_set_aux_buffers() - Check for gen < 9 and return early in intel_miptree_prepare_mcs() v4: Check for msaa_layput and number of samples to determine if lossless compression is to used. Otherwise one cannot distuingish between fast clear with and without compression. Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
* i965: Add flag telling if miptree is for client consumptionTopi Pohjolainen2016-05-121-0/+9
| | | | | | | | | | | | | | Consider later on adding specific disable flags such as MIPTREE_LAYOUT_DISABLE_AUX_MCS = 1 << 3, /* CCS_D */ MIPTREE_LAYOUT_DISABLE_AUX_CCS_E = 1 << 4, MIPTREE_LAYOUT_DISABLE_AUX = MIPTREE_LAYOUT_DISABLE_AUX_MCS | MIPTREE_LAYOUT_DISABLE_AUX_CCS_E, and equivalent boolean/enums into miptree. Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
* i965: Add helper for lossless compression supportTopi Pohjolainen2016-05-121-0/+4
| | | | | | | | | | | v2: Check explicitly against base type of GL_FLOAT instead of using _mesa_is_format_integer_color(). Otherwise we miss GL_UNSIGNED_NORMALIZED. v3 (Ben): Also call intel_miptree_supports_non_msrt_fast_clear() in order to really check everything. Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
* Revert "i965: Always use Y-tiled buffers on SKL+"Daniel Stone2016-05-091-2/+1
| | | | | | | | | | | | | | | | | | | This commit broke Weston, Mutter, and xf86-video-modesetting, on KMS. In order to use Y-tiled buffers, the kernel requires the tiling mode to be explicitly named through the I915_FORMAT_MOD_Y_TILED AddFB2 modifier; it disallows any attempt to infer the buffer's tiling mode. As the GBM API does not have a way to extract modifiers for a buffer, this commit broke all users of GBM on SKL+. Revert it for now, until we get a way to extract modifier information from GBM, and also let GBM users inform the implementation that it intends to use the modifiers. This reverts commit 6a0d036483caf87d43ebe2edd1905873446c9589. Signed-off-by: Daniel Stone <daniels@collabora.com> Acked-by: Ben Widawsky <ben@bwidawsk.net> Tested-by: Hans de Goede <hdegoede@redhat.com>
* i965: Always use Y-tiled buffers on SKL+Ben Widawsky2016-04-211-1/+2
| | | | | | | | | | | | | | | | Starting with Skylake, the display engine is capable of scanning out from Y-tiled buffers. As such, we can and should use Y-tiling for better efficiency. This also has the added benefit of being able to fast clear the winsys buffer. Note that the buffer allocation done for mipmaps will already never allocate an X-tiled buffer for GEN9. This has an almost universal positive impact on benchmarks, some improving by as much as 20%. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Declare input to mcs alignment calculation constantTopi Pohjolainen2016-04-211-1/+1
| | | | | Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Expose logic telling if non-msrt mcs is supportedTopi Pohjolainen2016-02-161-0/+8
| | | | | | | | | Alos use the opportunity to mark inputs constant. (Context has to be given as read-write to intel_miptree_supports_non_msrt_fast_clear() to support debug output). Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
* i965: Add a flag telling color resolve pass to ignore CCS_ETopi Pohjolainen2016-02-161-0/+9
| | | | | | | | | v2 (Ben): Use combination of msaa_layout and number of samples instead of introducing explicit type for lossless compression (intel_miptree_is_lossless_compressed()). Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
* i965: Add helper for detecting lossless compressionTopi Pohjolainen2016-02-161-0/+4
| | | | | Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
* i965: Add means for limiting color resolvesTopi Pohjolainen2016-02-131-1/+2
| | | | | | | | | | | | | | | | | Until now there has been only one type of color buffer that needs to resolved - namely single sampled fast clear. As even the sampler engine in GPU doesn't understand the associated meta data, the color values need to be always resolved prior to reading them. From SKL onwards there is new scheme supported called the lossless compression of single sampled color buffers. This is something that is understood by the sampling engine and therefore resolving of these types of buffers is not necessary before sampling. This patch adds means to make the distinction when considering if resolve is needed. Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
* i965/skl: Add fast color clear infrastructureBen Widawsky2015-11-201-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch was originally called: i965/skl: Enable fast color clears on SKL Skylake introduces some differences in the way that fast clears are programmed and in the restrictions for using fast clears. Since some of these are non-obvious, and fast clears are currently disabled globally, we can enable the simple stuff here and leave the weirder stuff and separately reviewable work. Based on a patch originally from Kristian. Note that within this patch the change in scaling factors could be achieved with this hunk instead. I've opted to keep things more like how the docs describe it however. --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -150,9 +150,13 @@ intel_get_non_msrt_mcs_alignment(struct brw_context *brw, /* In release builds, fall through */ case I915_TILING_Y: *width_px = 32 / mt->cpp; - *height = 4; + if (brw->gen >= 9) + *height = 2; + else + *height = 4; v2: Add braces for the multiline (Matt + Chad) Comment updates (requested by Chad) Modified commit message Commit message from Chad explaining the MCS height change (Chad) Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Neil Roberts <neil@linux.intel.com> Reviewed-by: Chad Versace <chad.versace@intel.com>
* i965/mt: Declare some functions as staticChad Versace2015-10-051-5/+1
| | | | | | | | intel_tiling_supports_non_msrt_mcs() and intel_miptree_is_fast_clear_capable() are not used outside of intel_mipmap_tree.c. Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
* i965/miptree: Add PRM references for most struct members (v2)Chad Versace2015-09-301-25/+154
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add comments that link the driver's miptree structures to the hardware structures documented in the PRM. This provides sorely needed orientation to developers new to the miptree code. And for miptree veterans, this clarifies some of the more obscure miptree data. For each driver struct field that closely corresponds to a hardware struct field, add a PRM reference to that hardware field's name. For example, struct intel_mipmap_tree { ... /** * @brief One of GL_TEXTURE_2D, GL_TEXTURE_2D_ARRAY, etc. * * @see RENDER_SURFACE_STATE.SurfaceType * @see RENDER_SURFACE_STATE.SurfaceArray * @see 3DSTATE_DEPTH_BUFFER.SurfaceType */ GLenum target; ... }; Also annotate the INTEL_MSAA_LAYOUT_* enums with the name of the PRM sections that documents the layout. v2: Replace "2D subimage" with "slice", and define what a "slice" is. For Ben. Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com> (v1) Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com> (v1)
* i965/miptree: Rename align_w,align_h -> halign,valignChad Versace2015-09-301-4/+14
| | | | | | | | | | | | | | | | | | | The values of intel_mipmap_tree::align_w and ::align_h correspond to the hardware enums HALIGN_* and VALIGN_*. See the confusion? align_h != HALIGN align_h == VALIGN Reduce the confusion by renaming the variables to match the hardware enum names: git ls-files | xargs sed -i -e 's/align_w/halign/g' \ -e 's/align_h/valign/g' Suggested-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Ben Widawsky <benjamin.widawsky@intel.com> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
* i965/miptree: Rename intel_miptree_map::mt -> ::linear_mt (v2)Chad Versace2015-09-301-1/+1
| | | | | | | | | | | Because that's what it is. It's an untiled, *linear* miptree. v2: - Add space after /*. - Use one comment per function argument. Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com> Acked-by: Ben Widawsky <benjamin.widawsky@intel.com>
* i965/miptree: Fix comments for map modeChad Versace2015-09-301-1/+1
| | | | | | | | | The comment for intel_miptree_map::mode claimed that it was a bitmask of GL_MAP_{READ,WRITE,INVALIDATE}_BIT. In reality, the bitmask may include any of {GL,BRW}_MAP_*_BIT. Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com> Acked-by: Ben Widawsky <benjamin.widawsky@intel.com>
* i965/miptree: More comments for BRW_MAP_DIRECT_BIT (v2)Chad Versace2015-09-301-1/+3
| | | | | | | | Clarify that this bit extends the set of GL_MAP_*_BIT enums. Also fix typo of "temporary". Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com> Acked-by: Ben Widawsky <benjamin.widawsky@intel.com>
* i965: Rename intel_miptree_get_dimensions_for_image()Anuj Phogat2015-09-281-2/+2
| | | | | | | | | | | This function isn't specific to miptrees. So, drop the "miptree" from function name. V3: Add a comment explaining how the 1D Array texture height and depth is interpreted by Intel hardware. Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Chad Versace <chad.versace@intel.com>
* i965: Use intel_get_tile_dims() to get tile masksAnuj Phogat2015-09-281-3/+3
| | | | | | | | | | | | | | | This will require change in the parameters passed to intel_miptree_get_tile_masks(). V2: Rearrange the order of parameters. (Ben) Change the name to intel_get_tile_masks(). (Topi) V3: Use temporary variables in intel_get_tile_masks() for clarity. Fix mask_y computation. Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Chad Versace <chad.versace@intel.com>
* i965: Add a helper function intel_get_tile_dims()Anuj Phogat2015-09-281-0/+4
| | | | | | | | | | | | | | V2: - Do the tile width/height computations in the new helper function and use it later in intel_miptree_get_tile_masks(). - Change the name to intel_get_tile_dims(). V3: Return the tile_h in number of rows in place of bytes. Document the units of tile_w, tile_h parameters. Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Chad Versace <chad.versace@intel.com>
* i965: Make intel_miptree_map_raw staticIan Romanick2015-09-101-6/+0
| | | | | | | | | | This hasn't been used outside intel_mipmap_tree.c since d5d4ba9 started using meta instead of the blitter for PBO TexSubImage. While we're here, remove the unused brw parameter from the function formerly known as intel_miptree_unmap_raw. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
* i915, i965: Silence unused parameter warnings in intel_mipmap_tree.hIan Romanick2015-09-101-0/+4
| | | | | | | | | | | | | | | | | | | These only occurred in release builds, but they occurred in every file that included intel_mipmap_tree.h. Lots of spam. :( intel_mipmap_tree.h: In function 'intel_miptree_check_level_layer': intel_mipmap_tree.h:595:59: warning: unused parameter 'mt' [-Wunused-parameter] intel_miptree_check_level_layer(struct intel_mipmap_tree *mt, ^ intel_mipmap_tree.h:596:42: warning: unused parameter 'level' [-Wunused-parameter] uint32_t level, ^ intel_mipmap_tree.h:597:42: warning: unused parameter 'layer' [-Wunused-parameter] uint32_t layer) ^ Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
* i965: Silence unused parameter warnings in intel_mipmap_tree.cIan Romanick2015-09-101-2/+1
| | | | | | | | | | | | | | | | | | | | | | The target parameter of compute_msaa_layout appears to be unused since 83b83fb when support for CMS textures was added for Gen7. The brw parameter of intel_get_non_msrt_mcs_alignment appears to be unused since e92fbdc when the GEN check (along with the "can we fast clear" decision) was moved to a different function. intel_mipmap_tree.c: In function 'compute_msaa_layout': intel_mipmap_tree.c:62:73: warning: unused parameter 'target' [-Wunused-parameter] compute_msaa_layout(struct brw_context *brw, mesa_format format, GLenum target, ^ intel_mipmap_tree.c: In function 'intel_get_non_msrt_mcs_alignment': intel_mipmap_tree.c:143:54: warning: unused parameter 'brw' [-Wunused-parameter] intel_get_non_msrt_mcs_alignment(struct brw_context *brw, ^ Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com> Cc: Ben Widawsky <benjamin.widawsky@intel.com>
* i965: Fix typos in licenseIan Romanick2015-09-101-2/+2
| | | | | | | | | | | | | | | | grep -lr 'sub license' | while read f; do \ sed --in-place -e 's/sub license/sublicense/' $f ;\ done grep -lr 'NON-INFRINGEMENT' | while read f; do \ sed --in-place -e 's/NON-INFRINGEMENT/NONINFRINGEMENT/' $f ;\ done As noted by Matt, both of these changes match the MIT license text found at http://opensource.org/licenses/MIT. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Acked-by: Matt Turner <mattst88@gmail.com>
* i965: Remove horizontal bars from file header commentsIan Romanick2015-09-101-4/+2
| | | | | | | Why was that ever a thing? Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Acked-by: Matt Turner <mattst88@gmail.com>
* i965: change the meaning of cpp for compressed texturesNanley Chery2015-08-261-1/+1
| | | | | | | | | | | | | | | | | | | | An ASTC block takes up 16 bytes for all block width and height configurations. This size is not integrally divisible by all ASTC block widths. Therefore cpp is changed to mean bytes per block if the texture is compressed. Because the original definition was bytes per block divided by block width, all references to the mipmap width must be divided the block width. This keeps the address calculation formulas consistent. For example, the units for miptree_level x_offset and miptree total_width has changed from pixels to blocks. v2: reuse preexisting ALIGN_NPOT macro located in an i965 driver file. v3: move ALIGN_NPOT into seperate commit. simplify cpp assignment in copy_image_with_blitter(). update miptree width and offset variables in: intel_miptree_copy_slice(), intel_miptree_map_gtt(), and brw_miptree_layout_texture_3d(). Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com> Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
* i965: Rename MIPTREE_LAYOUT_ALLOC_* -> MIPTREE_LAYOUT_TILING_*.Matt Turner2015-08-061-4/+4
| | | | | | | | | Ben suggested that I rename MIPTREE_LAYOUT_ALLOC_ANY_TILED since it needed to include no tiling at all, but the name MIPTREE_LAYOUT_ALLOC_ANY is pretty nondescriptive. We can avoid confusion by replacing "ALLOC" with "TILING" in the identifiers. Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
* i965: Correct a mistake that always forced texture tiling.Matt Turner2015-08-061-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Regression since commit 3a31876600, when tiling modes were moved into layout_flags. The relevant enum values are MIPTREE_LAYOUT_ALLOC_YTILED = 1 << 5 MIPTREE_LAYOUT_ALLOC_XTILED = 1 << 6 MIPTREE_LAYOUT_ALLOC_ANY_TILED = MIPTREE_LAYOUT_ALLOC_YTILED | MIPTREE_LAYOUT_ALLOC_XTILED MIPTREE_LAYOUT_ALLOC_LINEAR = 1 << 7 so the expression (layout_flags & MIPTREE_LAYOUT_ALLOC_ANY_TILED) can never produce a value of MIPTREE_LAYOUT_ALLOC_LINEAR. The enum this replaced was enum intel_miptree_tiling_mode { INTEL_MIPTREE_TILING_ANY, INTEL_MIPTREE_TILING_Y, INTEL_MIPTREE_TILING_NONE, }; where "ANY" means "Y" or "NONE" (i.e., linear). As such, remove the unused (and worse, unhandled) MIPTREE_LAYOUT_ALLOC_XTILED and redefine MIPTREE_LAYOUT_ALLOC_ANY_TILED to mean what it did before. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91513 Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
* i965: Push miptree tiling request into flagsBen Widawsky2015-07-161-8/+7
| | | | | | | | | | | | | | | | | | | | | With the last few patches a way was provided to influence lower layer miptree layout and allocation decisions via flags (replacing bools). For simplicity, I chose not to touch the tiling requests because the change was slightly less mechanical than replacing the bools. The goal is to organize the code so we can continue to add new parameters and tiling types while minimizing risk to the existing code, and not having to constantly add new function parameters. v2: Rebased on Anuj's recent Yf/Ys changes Fix non-msrt MCS allocation (was only happening in gen8 case before) v3: small fix in assertion requested by Chad v4: Use parens to get the order right from v3. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* Revert "i965: Push miptree tiling request into flags"Ben Widawsky2015-07-161-7/+8
| | | | This reverts commit 51e8d549e110f86cb7107cf712843aebd956fb9a.
* i965: Push miptree tiling request into flagsBen Widawsky2015-07-161-8/+7
| | | | | | | | | | | | | | | | | | | | | With the last few patches a way was provided to influence lower layer miptree layout and allocation decisions via flags (replacing bools). For simplicity, I chose not to touch the tiling requests because the change was slightly less mechanical than replacing the bools. The goal is to organize the code so we can continue to add new parameters and tiling types while minimizing risk to the existing code, and not having to constantly add new function parameters. v2: Rebased on Anuj's recent Yf/Ys changes Fix non-msrt MCS allocation (was only happening in gen8 case before) v3: small fix in assertion requested by Chad Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> (v2) Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com> (v2) Reviewed-by: Chad Versace <chad.versace@intel.com> (v2)
* i965/gen8: Correct HALIGN for AUX surfacesBen Widawsky2015-06-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This restriction was attempted in this commit: commit 47053464630888f819ef8cc44278f1a1220159b9 Author: Anuj Phogat <anuj.phogat@gmail.com> Date: Fri Feb 13 11:21:21 2015 -0800 i965/gen8: Use HALIGN_16 if MCS is enabled for non-MSRT However, the commit itself doesn't achieve the desired goal as determined by the asserts which the next patch adds. mcs_mt is NULL (never set) we're in the process of allocating the mcs_mt miptree when we get to this function. I didn't check, but perhaps this would work with blorp, however, meta clears allocate the miptree structure (which AFAICT needs the alignment also) way before it allocates using meta clears where the renderbuffer is allocated way before the aux buffer. The restriction is referenced in a few places, but the most concise one [IMO] from the spec is for Gen9. Gen8 loosens the restriction in that it only requires this for non-msrt surface. When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E, HALIGN 16 must be used. With the code before the miptree layout flag rework (patches preceding this), accomplishing this workaround is very difficult. v2: bugfix: Don't set HALIGN16 for gens before 8 (Chad) v3: non-trivial rebase Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Cc: Neil Roberts <neil@linux.intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Chad Versace <chad.versace@intel.com>
* i965: Extract tiling from fast clear decisionBen Widawsky2015-06-121-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are several constraints when determining if one can fast clear a surface. Some of these are alignment, pixel density, tiling formats, and others that vary by generation. The helper function which exists today does a suitable job, however it conflates "BO properties" with "Miptree properties" when using tiling. I consider the former to be attributes of the physical surface, things which are determined through BO allocation, and the latter being attributes which are derived from the API, and having nothing to do with the underlying surface. Determining tiling properties and creating miptrees are related operations (when we allocate a BO for a miptree) with some disjoint constraints. By extracting the decisions into two distinct choices (tiling vs. miptree properties), we gain flexibility throughout the code to make determinations about when we can or cannot fast clear strictly on the miptree. To signify this change, I've also renamed the function to indicate it is a distinction made on the miptree. I am torn as to whether or not it was a good idea to remove "non_msrt" since it's a really nice thing for grep. v2: Reword some comments (Chad) intel_is_non_msrt_mcs_tile_supported->intel_tiling_supports_non_msrt_mcs (Chad) Make full if ladder for gens in above function (Chad) Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Cc: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
* i965: Consolidate certain miptree params to flagsBen Widawsky2015-06-121-5/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I think pretty much everyone agrees that having more than a single bool as a function argument is bordering on a bad idea. What sucks about the current code is in several instances it's necessary to propagate these boolean selections down to lower layers of the code. This requires plumbing (mechanical, but still churn) pretty much all of the miptree functions each time. By introducing the flags paramater, it is possible to add miptree constraints very easily. The use of this, as is already the case, is sometimes we have some information at the time we create the miptree that needs to be known all the way at the lowest levels of the create/allocation, disable_aux_buffers is currently one such example. There will be another example coming up in a few patches. v2: Tab fix. (Ben) Long line fixes (Topi) Use anonymous enum instead of #define for layout flags (Chad) Use 'X != 0' instead of !!X (everyone except Chad) v3: Some non-trivial conflict resolution on top of Anuj's patches. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Cc: "Pohjolainen, Topi" <topi.pohjolainen@intel.com> Reviewed-by: Chad Versace <chad.versace@intel.com> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* i965/gen9: Set tiled resource mode for the miptreeAnuj Phogat2015-06-081-0/+8
| | | | | Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965: Move intel_miptree_choose_tiling() to brw_tex_layout.cAnuj Phogat2015-06-081-8/+0
| | | | | | | | | and change the name to brw_miptree_choose_tiling(). V3: Remove redundant function parameters. (Topi) Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965: Choose tiling in brw_miptree_layout() functionAnuj Phogat2015-06-081-1/+13
| | | | | | | This refactoring is required by later patches in this series. Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965: Add helper functions to calculate the slice pitch of an array or 3D ↵Francisco Jerez2015-04-271-0/+18
| | | | miptree.
generated by cgit v1.1 at 2024-09-12 01:12:26 +0000