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Emulating each instruction of the software refill handler
has a significant impact on the overall performance of QEMU because
of the overhead of emulating the various CP0 instructions to accurately
reflect the machine state. Running the software TLB handler takes
the equivalent of 1000's of machine cycles.
This patch implements a pseudo hardware TLB refill handler
that significantly reduces the impact of refilling the TLB
to bring it more inline with what would be observed on a real target.
Signed-off-by: Steven Hill <sjhill@mips.com>
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Yajin <yajin@mips.com.cn>
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Avoid truncation of 64-bit host addresses for 32-bit Mips physaddrs.
Revert workaround I17fe688d19e3cd7f328721e6363bacd6e6689ca;
allow emulator to again default to emulator64-mips.
Change-Id: I0c83d8bf60fc52a758b84d8131b2bad53375aa61
Signed-off-by: Duane Sand <duanes@mips.com>
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Clang and llvm-gcc don't support global register variable (GRV) crucial
to emulator (where a register is reserved to point to target architecture
state for better code-gen). Clang and llvm-gcc are provided in recent
Xcode to replace the original gcc with GRV support. MacOSX developers
may accidentally install newer Xcode and break emulator.
This CL allows emulator (and the rest of Android tree) to build but forces
emulator to quit if it's built w/o GRV support. Developers build
Android tree with clang or llvm-gcc can still get good system image,
but they have to use emulators built the other way or from SDKs to run it.
Related CL & bug entry:
https://android-review.googlesource.com/#/c/33011
http://code.google.com/p/android/issues/detail?id=32577
Change-Id: Ia585dd7bf9783e2ff4c114b4f0ec20b89684ab57
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Change-Id: I3ddfd3de165575c52a76cf9acee1e304d42562cf
Signed-off-by: Chris Dearman <chris@mips.com>
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This applies to round, trunc, ceil and floor instructions
Change-Id: I4a5f1619ecd8fe2d7ce508f8e569be129a8b1e34
Signed-off-by: Chris Dearman <chris@mips.com>
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Basic Goldfish support for MIPS.
Also, Fix host CPU consumption when guest is idle
When the CPU is in wait state, do not wake-up if an interrupt can't be
taken. This avoid host CPU running at 100% if a device (e.g. timer) has
an interrupt line left enabled.
Also factorize code to check if interrupts are enabled in
cpu_mips_hw_interrupts_pending().
CPU consumption based on a patch from
Edgar E. Iglesias <edgar.iglesias@gmail.com>
Change-Id: Ie8371c8d0c9af1e0c8ba4cac419979350de0f5d9
Signed-off-by: yajin <yajin@mips.com.cm>
Signed-off-by: Douglas Leung <douglas@mips.com>
Signed-off-by: Bhanu Chetlapalli <bhanu@mips.com>
Signed-off-by: Chris Dearman <chris@mips.com>
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Change-Id: Icd617cb91fe87a6f88566dd57b6405b216ca3570
Signed-off-by: Chris Dearman <chris@mips.com>
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From v0.12.5 tag at git://git.sv.gnu.org/qemu.git
CommitID: 174f225e9d62e8f3002e274e4f718bd2a967fbf4
Change-Id: I35b49a4319cee4b69cf9da4e5af1f43327e21056
Signed-off-by: Chris Dearman <chris@mips.com>
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