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| author | Gustavo Diaz Prado <a0273371@ti.com> | 2012-08-31 15:11:37 -0500 |
|---|---|---|
| committer | Daniel Levin <dendy@ti.com> | 2012-11-28 21:16:24 +0200 |
| commit | 9374529441688bd5e22ac60b7725c1485a33307c (patch) | |
| tree | 96ab700fda3c2608d3812290fa0f8c48764d0bb2 /hwc | |
| parent | 4c1eea2cdbd44b2f39db91fbe078a348d927904b (diff) | |
| download | hardware_ti_omap4-9374529441688bd5e22ac60b7725c1485a33307c.zip hardware_ti_omap4-9374529441688bd5e22ac60b7725c1485a33307c.tar.gz hardware_ti_omap4-9374529441688bd5e22ac60b7725c1485a33307c.tar.bz2 | |
hwc: Fix incorrect tiler memory available check
When the buffers composed with DSS pipes use exactly the tiler1d
memory available (like 4 fullscreen layers on Tablet 2), the
prepare operation fails to assign a DSS pipe to the last buffer
(even if it was possible) making it to be rendered by the GPU
but without a pipe to show it. This patch fixes the incorrect
memory check that caused this problem.
Change-Id: Ibb147a468aa2e1622600a56f581013dc1e517777
Signed-off-by: Gustavo Diaz Prado <a0273371@ti.com>
Signed-off-by: Jonas Larsson <jonas.larsson@ti.com>
Diffstat (limited to 'hwc')
| -rw-r--r-- | hwc/hwc.c | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -1758,7 +1758,7 @@ static int omap4_hwc_prepare(struct hwc_composer_device *dev, hwc_layer_list_t* is_protected(layer) || is_upscaled_NV12(hwc_dev, layer) || (hwc_dev->ext.current.docking && hwc_dev->ext.current.enabled && dockable(layer))) && - mem_used + mem1d(handle) < limits.tiler1d_slot_size && + mem_used + mem1d(handle) <= limits.tiler1d_slot_size && /* can't have a transparent overlay in the middle of the framebuffer stack */ !(is_BLENDED(layer) && fb_z >= 0)) { |