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| author | Olof Johansson <olof@lixom.net> | 2013-01-27 22:33:42 -0800 |
|---|---|---|
| committer | Olof Johansson <olof@lixom.net> | 2013-01-27 22:33:42 -0800 |
| commit | 3394d8977e61613b91b4e4e3268f96feba0a7293 (patch) | |
| tree | 9b21636d73e4d8be64856040bc1a0a674ecd3532 /arch/arm/mach-pxa/smemc.c | |
| parent | 6b914c998787d65022e80d6262dfd0edef58cadb (diff) | |
| parent | eea6e39b916dd282c7fa4629be8934b5ad60e62b (diff) | |
| download | kernel_goldelico_gta04-3394d8977e61613b91b4e4e3268f96feba0a7293.zip kernel_goldelico_gta04-3394d8977e61613b91b4e4e3268f96feba0a7293.tar.gz kernel_goldelico_gta04-3394d8977e61613b91b4e4e3268f96feba0a7293.tar.bz2 | |
Merge branch 'armsoc/fix' of git://github.com/hzhuang1/linux into next/cleanup
A couple of PXA fixes that aren't critical enough for 3.9. From Haojian
Zhuang.
* 'armsoc/fix' of git://github.com/hzhuang1/linux:
ARM: pxa: Minor naming fixes in spitz.c
ARM: PXA3xx: program the CSMSADRCFG register
ARM: palmtreo: fix #ifdefs for leds-gpio device
ARM: palmtreo: fix lcd initilialization on treo680
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/mach-pxa/smemc.c')
| -rw-r--r-- | arch/arm/mach-pxa/smemc.c | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/arch/arm/mach-pxa/smemc.c b/arch/arm/mach-pxa/smemc.c index 7992305..f38aa89 100644 --- a/arch/arm/mach-pxa/smemc.c +++ b/arch/arm/mach-pxa/smemc.c @@ -40,6 +40,8 @@ static void pxa3xx_smemc_resume(void) __raw_writel(csadrcfg[1], CSADRCFG1); __raw_writel(csadrcfg[2], CSADRCFG2); __raw_writel(csadrcfg[3], CSADRCFG3); + /* CSMSADRCFG wakes up in its default state (0), so we need to set it */ + __raw_writel(0x2, CSMSADRCFG); } static struct syscore_ops smemc_syscore_ops = { @@ -49,8 +51,19 @@ static struct syscore_ops smemc_syscore_ops = { static int __init smemc_init(void) { - if (cpu_is_pxa3xx()) + if (cpu_is_pxa3xx()) { + /* + * The only documentation we have on the + * Chip Select Configuration Register (CSMSADRCFG) is that + * it must be programmed to 0x2. + * Moreover, in the bit definitions, the second bit + * (CSMSADRCFG[1]) is called "SETALWAYS". + * Other bits are reserved in this register. + */ + __raw_writel(0x2, CSMSADRCFG); + register_syscore_ops(&smemc_syscore_ops); + } return 0; } |